test/frontend/static/quotes/code_systemverilog.json

{
  "language": "code_systemverilog",
  "groups": [
    [0, 500],
    [501, 4000],
    [4001, 8000],
    [8001, 15000]
  ],
  "quotes": [
    {
      "text": "module fwrisc_alu (\n\tinput clock,\n\tinput reset,\n\tinput[31:0] op_a,\n\tinput[31:0] op_b,\n\tinput[3:0] op,\n\toutput reg[31:0] out);\n\tparameter [3:0]\n\t\tOP_ADD = 4'd0,\n\t\tOP_SUB = (OP_ADD+4'd1),\n\t\tOP_AND = (OP_SUB+4'd1),\n\t\tOP_OR = (OP_AND+4'd1),\n\t\tOP_CLR = (OP_OR+4'd1),\n\t\tOP_EQ = (OP_CLR+4'd1),\n\t\tOP_NE = (OP_EQ+4'd1),\n\t\tOP_LT = (OP_NE+4'd1),\n\t\tOP_GE = (OP_LT+4'd1),\n\t\tOP_LTU = (OP_GE+4'd1),\n\t\tOP_GEU = (OP_LTU+4'd1),\n\t\tOP_OPA = (OP_GEU+4'd1),\n\t\tOP_OPB = (OP_OPA+4'd1),\n\t\tOP_XOR = (OP_OPB+4'd1);\n\talways @* begin\n\t\tcase (op)\n\t\t\tOP_ADD: out = op_a + op_b;\n\t\t\tOP_SUB: out = op_a - op_b;\n\t\t\tOP_AND: out = op_a & op_b;\n\t\t\tOP_OR: out = op_a | op_b;\n\t\t\tOP_CLR: out = op_b ^ (op_a & op_b);\n\t\t\tOP_EQ: out = {31'b0, op_a == op_b};\n\t\t\tOP_NE: out = {31'b0, op_a != op_b};\n\t\t\tOP_LT: out = {31'b0, $signed(op_a) < $signed(op_b)};\n\t\t\tOP_GE: out = {31'b0, $signed(op_a) >= $signed(op_b)};\n\t\t\tOP_LTU: out = {31'b0, op_a < op_b};\n\t\t\tOP_GEU: out = {31'b0, op_a >= op_b};\n\t\t\tOP_OPA: out = op_a;\n\t\t\tOP_OPB: out = op_b;\n\t\t\tdefault: out = op_a ^ op_b;\n\t\tendcase\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_alu",
      "length": 1046,
      "id": 1
    },
    {
      "text": "module fwrisc_c_decode(\n\tinput clock,\n\tinput reset,\n\tinput[15:0] instr_i,\n\toutput reg[31:0] instr);\n\tparameter [6:0]\n\t\tOPCODE_OP_IMM = 7'b0010011,\n\t\tOPCODE_LOAD = 7'b0000011,\n\t\tOPCODE_JAL = 7'b1101111,\n\t\tOPCODE_LUI = 7'b0110111,\n\t\tOPCODE_OP = 7'b0110011,\n\t\tOPCODE_BRANCH = 7'b1100011,\n\t\tOPCODE_JALR = 7'b1100111,\n\t\tOPCODE_STORE = 7'b0100011;\n\talways @* begin\n\t\tinstr = 0;\n\t\tcase (instr_i[1:0])\n\t\t\t2'b00: begin\n\t\t\t\tcase (instr_i[15:13])\n\t\t\t\t\t3'b000: begin\n\t\t\t\t\t\tinstr = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5],\n\t\t\t\t\t\t\t\tinstr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}};\n\t\t\t\t\tend\n\t\t\t\t\t3'b010: begin\n\t\t\t\t\t\tinstr = {5'b0, instr_i[5], instr_i[12:10], instr_i[6],\n\t\t\t\t\t\t\t\t2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}};\n\t\t\t\t\tend\n\t\t\t\t\t3'b110: begin\n\t\t\t\t\t\tinstr = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],\n\t\t\t\t\t\t\t\t2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],\n\t\t\t\t\t\t\t\t2'b00, {OPCODE_STORE}};\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t2'b01: begin\n\t\t\t\tcase (instr_i[15:13])\n\t\t\t\t\t3'b000: begin\n\t\t\t\t\t\tinstr = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2],\n\t\t\t\t\t\t\t\tinstr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n\t\t\t\t\tend\n\n\t\t\t\t\t3'b001, 3'b101: begin\n\t\t\t\t\t\tinstr = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],\n\t\t\t\t\t\t\t\tinstr_i[7], instr_i[2], instr_i[11], instr_i[5:3],\n\t\t\t\t\t\t\t\t{9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}};\n\t\t\t\t\tend\n\t\t\t\t\t3'b010: begin\n\t\t\t\t\t\tinstr = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0,\n\t\t\t\t\t\t\t\t3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n\t\t\t\t\tend\n\t\t\t\t\t3'b011: begin\n\t\t\t\t\t\tinstr = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};\n\t\t\t\t\t\tif (instr_i[11:7] == 5'h02) begin\n\t\t\t\t\t\t\tinstr = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],\n\t\t\t\t\t\t\t\t\tinstr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}};\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\tcase (instr_i[11:10])\n\t\t\t\t\t\t\t2'b00,\n\t\t\t\t\t\t\t2'b01: begin\n\t\t\t\t\t\t\t\tinstr = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7],\n\t\t\t\t\t\t\t\t\t\t3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t2'b10: begin\n\t\t\t\t\t\t\t\tinstr = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7],\n\t\t\t\t\t\t\t\t\t\t3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t2'b11: begin\n\t\t\t\t\t\t\t\tcase ({instr_i[12], instr_i[6:5]})\n\t\t\t\t\t\t\t\t\t3'b000: begin\n\t\t\t\t\t\t\t\t\t\tinstr = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7],\n\t\t\t\t\t\t\t\t\t\t\t\t3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}};\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t3'b001: begin\n\t\t\t\t\t\t\t\t\t\tinstr = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100,\n\t\t\t\t\t\t\t\t\t\t\t\t2'b01, instr_i[9:7], {OPCODE_OP}};\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t3'b010: begin\n\t\t\t\t\t\t\t\t\t\tinstr = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110,\n\t\t\t\t\t\t\t\t\t\t\t\t2'b01, instr_i[9:7], {OPCODE_OP}};\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t3'b011: begin\n\t\t\t\t\t\t\t\t\t\tinstr = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111,\n\t\t\t\t\t\t\t\t\t\t\t\t2'b01, instr_i[9:7], {OPCODE_OP}};\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\t\t3'b110, 3'b111: begin\n\t\t\t\t\t\tinstr = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01,\n\t\t\t\t\t\t\t\tinstr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3],\n\t\t\t\t\t\t\t\tinstr_i[12], {OPCODE_BRANCH}};\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t2'b10: begin\n\t\t\t\tcase (instr_i[15:13])\n\t\t\t\t\t3'b000: begin\n\t\t\t\t\t\tinstr = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}};\n\t\t\t\t\tend\n\t\t\t\t\t3'b010: begin\n\t\t\t\t\t\tinstr = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02,\n\t\t\t\t\t\t\t\t3'b010, instr_i[11:7], OPCODE_LOAD};\n\t\t\t\t\tend\n\t\t\t\t\t3'b100: begin\n\t\t\t\t\t\tif (instr_i[12] == 1'b0) begin\n\t\t\t\t\t\t\tif (instr_i[6:2] != 5'b0) begin\n\t\t\t\t\t\t\t\tinstr = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tinstr = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tif (instr_i[6:2] != 5'b0) begin\n\t\t\t\t\t\t\t\tinstr = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tif (instr_i[11:7] == 5'b0) begin\n\t\t\t\t\t\t\t\t\tinstr = {32'h00_10_00_73};\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tinstr = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\t3'b110: begin\n\t\t\t\t\t\tinstr = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010,\n\t\t\t\t\t\t\t\tinstr_i[11:9], 2'b00, {OPCODE_STORE}};\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tdefault: begin\n\t\t\t\tinstr = instr_i;\n\t\t\tend\n\t\tendcase\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_c_decode",
      "length": 4445,
      "id": 2
    },
    {
      "text": "module fwrisc_decode #(\n\tparameter ENABLE_COMPRESSED=1\n\t)(\n\tinput clock,\n\tinput reset,\n\tinput fetch_valid,\n\toutput decode_complete,\n\tinput[31:0] instr_i,\n\tinput instr_c,\n\tinput[31:0] pc,\n\toutput reg[5:0] ra_raddr,\n\tinput[31:0] ra_rdata,\n\toutput reg[5:0] rb_raddr,\n\tinput[31:0] rb_rdata,\n\toutput decode_valid,\n\tinput exec_complete,\n\toutput reg[31:0] op_a,\n\toutput reg[31:0] op_b,\n\toutput reg[31:0] op_c,\n\toutput[3:0] op,\n\toutput reg[5:0] rd_raddr,\n\toutput reg[4:0] op_type);\n\tparameter [4:0]\n\t\tOP_TYPE_ARITH = 5'd0,\n\t\tOP_TYPE_BRANCH = (OP_TYPE_ARITH+5'd1),\n\t\tOP_TYPE_LDST = (OP_TYPE_BRANCH+5'd1),\n\t\tOP_TYPE_MDS = (OP_TYPE_LDST+5'd1),\n\t\tOP_TYPE_JUMP = (OP_TYPE_MDS+5'd1),\n\t\tOP_TYPE_SYSTEM = (OP_TYPE_JUMP+5'd1),\n\t\tOP_TYPE_CSR = (OP_TYPE_SYSTEM+5'd1);\n\tparameter [3:0]\n\t\tOP_ADD = 4'd0,\n\t\tOP_SUB = (OP_ADD+4'd1),\n\t\tOP_AND = (OP_SUB+4'd1),\n\t\tOP_OR = (OP_AND+4'd1),\n\t\tOP_CLR = (OP_OR+4'd1),\n\t\tOP_EQ = (OP_CLR+4'd1),\n\t\tOP_NE = (OP_EQ+4'd1),\n\t\tOP_LT = (OP_NE+4'd1),\n\t\tOP_GE = (OP_LT+4'd1),\n\t\tOP_LTU = (OP_GE+4'd1),\n\t\tOP_GEU = (OP_LTU+4'd1),\n\t\tOP_OPA = (OP_GEU+4'd1),\n\t\tOP_OPB = (OP_OPA+4'd1),\n\t\tOP_XOR = (OP_OPB+4'd1);\n\tparameter [3:0]\n\t\tOP_SLL = 4'd0,\n\t\tOP_SRL = (OP_SLL + 4'd1),\n\t\tOP_SRA = (OP_SRL + 4'd1),\n\t\tOP_MUL = (OP_SRA + 4'd1),\n\t\tOP_MULH = (OP_MUL + 4'd1),\n\t\tOP_MULS = (OP_MULH + 4'd1),\n\t\tOP_MULSH = (OP_MULS + 4'd1),\n\t\tOP_DIV = (OP_MULSH + 4'd1),\n\t\tOP_REM = (OP_DIV + 4'd1),\n\t\tOP_NUM_MDS = (OP_REM + 4'd1);\n\tparameter [3:0]\n\t\tOP_LB = 4'd0,\n\t\tOP_LH = (OP_LB+4'd1),\n\t\tOP_LW = (OP_LH+4'd1),\n\t\tOP_LBU = (OP_LW+4'd1),\n\t\tOP_LHU = (OP_LBU+4'd1),\n\t\tOP_SB = (OP_LHU + 4'd1),\n\t\tOP_SH = (OP_SB + 4'd1),\n\t\tOP_SW = (OP_SH + 4'd1),\n\t\tOP_NUM_MEM = (OP_SW + 4'd1);\n\tparameter [5:0]\n\t\tCSR_BASE_Q0 = 6'h20,\n\t\tCSR_MVENDORID = (CSR_BASE_Q0 + 1'd1),\n\t\tCSR_MARCHID = (CSR_MVENDORID + 1'd1),\n\t\tCSR_MIMPID = (CSR_MARCHID + 1'd1),\n\t\tCSR_MHARTID = (CSR_MIMPID + 1'd1),\n\t\tCSR_BASE_Q1 = 6'h28,\n\t\tCSR_MSTATUS = (CSR_BASE_Q1 + 1'd0),\n\t\tCSR_MISA = (CSR_MSTATUS + 1'd1),\n\t\tCSR_MEDELEG = (CSR_MISA + 1'd1),\n\t\tCSR_MIDELEG = (CSR_MEDELEG + 1'd1),\n\t\tCSR_MIE = (CSR_MIDELEG + 1'd1),\n\t\tCSR_MTVEC = (CSR_MIE + 1'd1),\n\t\tCSR_MCOUNTEREN = (CSR_MTVEC + 1'd1),\n\t\tCSR_BASE_Q2 = 6'h30,\n\t\tCSR_MSCRATCH = (CSR_BASE_Q2 + 1'd0),\n\t\tCSR_MEPC = (CSR_MSCRATCH + 1'd1),\n\t\tCSR_MCAUSE = (CSR_MEPC + 1'd1),\n\t\tCSR_MTVAL = (CSR_MCAUSE + 1'd1),\n\t\tCSR_MIP = (CSR_MTVAL + 1'd1),\n\t\tCSR_BASE_Q3 = 6'h38,\n\t\tCSR_MCYCLE = (CSR_BASE_Q3 + 1'd0),\n\t\tCSR_MCYCLEH = (CSR_MCYCLE + 1'd1),\n\t\tCSR_MINSTRET = (CSR_MCYCLEH + 1'd1),\n\t\tCSR_MINSTRETH = (CSR_MINSTRET + 1'd1),\n\t\tCSR_DEP_LO = (CSR_MINSTRETH + 1'd1),\n\t\tCSR_DEP_HI = (CSR_DEP_LO + 1'd1),\n\t\tCSR_SOFT_RESET = (CSR_DEP_HI + 1'd1);\n\tparameter [3:0]\n\t\tOP_TYPE_ECALL = 1'd0,\n\t\tOP_TYPE_EBREAK = (OP_TYPE_ECALL + 1'd1),\n\t\tOP_TYPE_ERET = (OP_TYPE_EBREAK + 1'd1);\n\twire[31:0] instr;\n\twire[31:0] imm_jump = $signed({instr[31], instr[19:12], instr[20], instr[30:21],1'b0});\n\twire[31:0] auipc_imm_31_12 = {instr[31:12], {12{1'b0}}};\n\twire[31:0] imm_11_0 = $signed({instr[31:20]});\n\twire[31:0] st_imm_11_0 = $signed({instr[31:25], instr[11:7]});\n\treg[31:0] imm_lui;\n\twire[31:0] imm_branch = $signed({instr[31], instr[7], instr[30:25], instr[11:8], 1'b0});\n\treg[4:0] op_type_w;\n\treg[3:0] op_w;\n\treg decode_valid_r;\n\tgenerate\n\t\tif (ENABLE_COMPRESSED) begin\n\t\t\twire [31:0] instr_exp;\n\t\t\tfwrisc_c_decode u_c_decode (\n\t\t\t\t.clock (clock),\n\t\t\t\t.reset (reset),\n\t\t\t\t.instr_i (instr_i[15:0]),\n\t\t\t\t.instr (instr_exp));\n\t\t\tassign instr = (instr_c)?instr_exp:instr_i;\n\t\tend else begin\n\t\t\tassign instr = instr_i;\n\t\tend\n\tendgenerate\n\tparameter[3:0]\n\t\tI_TYPE_R = 4'd0,\n\t\tI_TYPE_I = (I_TYPE_R+4'd1),\n\t\tI_TYPE_S = (I_TYPE_I+4'd1),\n\t\tI_TYPE_B = (I_TYPE_S+4'd1),\n\t\tI_TYPE_U = (I_TYPE_B+4'd1),\n\t\tI_TYPE_J = (I_TYPE_U+4'd1),\n\t\tI_TYPE_L = (I_TYPE_J+4'd1),\n\t\tI_TYPE_SY = (I_TYPE_L+4'd1);\n\tparameter[3:0]\n\t\tCI_TYPE_CR = 4'd0,\n\t\tCI_TYPE_CR_P = (CI_TYPE_CR+4'd1),\n\t\tCI_TYPE_CI = (CI_TYPE_CR_P+4'd1),\n\t\tCI_TYPE_CI_P = (CI_TYPE_CI+4'd1),\n\t\tCI_TYPE_CSS = (CI_TYPE_CI_P+4'd1),\n\t\tCI_TYPE_CIW = (CI_TYPE_CSS+4'd1),\n\t\tCI_TYPE_CL = (CI_TYPE_CIW+4'd1),\n\t\tCI_TYPE_CS = (CI_TYPE_CL+4'd1),\n\t\tCI_TYPE_CB = (CI_TYPE_CS+4'd1),\n\t\tCI_TYPE_CJ = (CI_TYPE_CB+4'd1);\n\treg[2:0] i_type;\n\twire c_rs_rd_eq_0 = (instr[11:7] == 0);\n\twire c_rs_rd_eq_2 = (instr[11:7] == 2);\n\twire c_rs2_eq_0 = (|instr[6:2] == 0);\n\twire[5:0] c_rs1_rd_p = ({3'b001, instr[9:7]});\n\twire[5:0] c_rd_rs2_p = ({3'b001, instr[4:2]});\n\twire[5:0] c_rd_rs1 = instr[11:7];\n\treg[5:0] rd_raddr_w;\n\tassign op = op_w;\n\talways @* begin\n\t\top_w = 0;\n\t\trd_raddr_w = instr[11:7];\n\t\tcase (instr[6:4])\n\t\t\t3'b000: i_type = I_TYPE_L;\n\t\t\t3'b001: i_type = (instr[2])?I_TYPE_U:I_TYPE_I;\n\t\t\t3'b010: i_type = I_TYPE_S;\n\t\t\t3'b011: i_type = (instr[2])?I_TYPE_U:I_TYPE_R;\n\t\t\t3'b110: begin\n\t\t\t\tcase (instr[3:2])\n\t\t\t\t\t2'b11: i_type = I_TYPE_J;\n\t\t\t\t\t2'b01: i_type = I_TYPE_I;\n\t\t\t\t\tdefault: i_type = I_TYPE_B;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t3'b111: i_type = I_TYPE_SY;\n\t\t\tdefault: i_type = (instr[2])?I_TYPE_J:I_TYPE_B;\n\t\tendcase\n\t\tcase (instr[6:4])\n\t\t\t3'b000: op_type_w=(&instr[3:2])?OP_TYPE_ARITH:OP_TYPE_LDST;\n\t\t\t3'b001: begin\n\t\t\t\tif (instr[2]) begin\n\t\t\t\t\top_type_w = OP_TYPE_ARITH;\n\t\t\t\tend else if (instr[14:12] == 3'b101 || instr[14:12] == 3'b001) begin\n\t\t\t\t\top_type_w = OP_TYPE_MDS;\n\t\t\t\tend else begin\n\t\t\t\t\top_type_w = OP_TYPE_ARITH;\n\t\t\t\tend\n\t\t\tend\n\t\t\t3'b010: op_type_w = OP_TYPE_LDST;\n\t\t\t3'b011: begin\n\t\t\t\tif (instr[2]) begin\n\t\t\t\t\top_type_w = OP_TYPE_ARITH;\n\t\t\t\tend else if (instr[14:12] == 3'b101 || instr[14:12] == 3'b001 || instr[25]) begin\n\t\t\t\t\top_type_w = OP_TYPE_MDS;\n\t\t\t\tend else begin\n\t\t\t\t\top_type_w = OP_TYPE_ARITH;\n\t\t\t\tend\n\t\t\tend\n\t\t\t3'b110: op_type_w = (instr[2])?OP_TYPE_JUMP:OP_TYPE_BRANCH;\n\t\t\tdefault: begin\n\t\t\t\top_type_w = (|instr[14:12])?OP_TYPE_CSR:OP_TYPE_SYSTEM;\n\t\t\tend\n\t\tendcase\n\t\tcase (op_type_w)\n\t\t\tOP_TYPE_SYSTEM: ra_raddr = CSR_MEPC;\n\t\t\tdefault: ra_raddr = instr[19:15];\n\t\tendcase\n\t\tcase (op_type_w)\n\t\t\tOP_TYPE_CSR: begin\n\t\t\t\tcase (instr[31:24])\n\t\t\t\t\t8'hF1: rb_raddr = (CSR_BASE_Q0 | instr[23:20]);\n\t\t\t\t\t8'h30: rb_raddr = (CSR_BASE_Q1 | instr[23:20]);\n\t\t\t\t\t8'h34: rb_raddr = (CSR_BASE_Q2 | instr[23:20]);\n\t\t\t\t\t8'hB0: rb_raddr = (instr[21])?CSR_MINSTRET:CSR_MCYCLE;\n\t\t\t\t\t8'hB8: begin\n\t\t\t\t\t\trb_raddr = (instr[21])?CSR_MINSTRETH:CSR_MCYCLEH;\n\t\t\t\t\tend\n\t\t\t\t\t8'hBC: begin\n\t\t\t\t\t\tcase (instr[21:20])\n\t\t\t\t\t\t\t2'b00: rb_raddr = CSR_DEP_LO;\n\t\t\t\t\t\t\t2'b01: rb_raddr = CSR_DEP_HI;\n\t\t\t\t\t\t\tdefault: rb_raddr = CSR_SOFT_RESET;\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\t\tdefault: rb_raddr = 0;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tdefault: rb_raddr = instr[24:20];\n\t\tendcase\n\t\tcase (i_type)\n\t\t\tI_TYPE_R, I_TYPE_I, I_TYPE_B, I_TYPE_S: begin\n\t\t\t\top_a = ra_rdata;\n\t\t\tend\n\t\t\tI_TYPE_SY: begin\n\t\t\t\tif (instr[14]) begin\n\t\t\t\t\top_a = instr[19:15];\n\t\t\t\tend else begin\n\t\t\t\t\top_a = ra_rdata;\n\t\t\t\tend\n\t\t\tend\n\t\t\tI_TYPE_L: op_a = ra_rdata;\n\t\t\tI_TYPE_J: op_a = pc;\n\t\t\tI_TYPE_U: op_a = imm_lui;\n\t\t\tdefault: op_a = 0;\n\t\tendcase\n\t\tcase (i_type)\n\t\t\tI_TYPE_R, I_TYPE_S, I_TYPE_SY, I_TYPE_B: begin\n\t\t\t\top_b = rb_rdata;\n\t\t\tend\n\t\t\tI_TYPE_I: begin\n\t\t\t\tcase (instr[14:12])\n\t\t\t\t\t3'b101, 3'b001: begin\n\t\t\t\t\t\top_b = instr[24:20];\n\t\t\t\t\tend\n\t\t\t\t\t3'b011: begin\n\t\t\t\t\t\top_b = $signed(instr[31:20]);\n\t\t\t\t\tend\n\t\t\t\t\tdefault: op_b = imm_11_0;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tI_TYPE_L: op_b = rb_rdata;\n\t\t\tI_TYPE_U: begin\n\t\t\t\tif (instr[5]) begin\n\t\t\t\t\top_b = 32'b0;\n\t\t\t\tend else begin\n\t\t\t\t\top_b = pc;\n\t\t\t\tend\n\t\t\tend\n\t\t\tdefault: op_b = 32'b0;\n\t\tendcase\n\t\tcase (i_type)\n\t\t\tI_TYPE_B: op_c = imm_branch;\n\t\t\tI_TYPE_I,I_TYPE_L: op_c = imm_11_0;\n\t\t\tI_TYPE_S: op_c = st_imm_11_0;\n\t\t\tI_TYPE_J: op_c = imm_jump;\n\t\t\tI_TYPE_SY: begin\n\t\t\t\top_c = rb_raddr;\n\t\t\tend\n\t\t\tdefault: op_c = 32'b0;\n\t\tendcase\n\t\tcase (op_type)\n\t\t\tOP_TYPE_ARITH: begin\n\t\t\t\tif (instr[2]) begin\n\t\t\t\t\top_w = (instr[5])?OP_OPA:OP_ADD;\n\t\t\t\tend else begin\n\t\t\t\t\tcase (instr[14:12])\n\t\t\t\t\t\t3'b000: begin\n\t\t\t\t\t\t\tif (i_type == I_TYPE_R && instr[30]) begin\n\t\t\t\t\t\t\t\top_w = OP_SUB;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\top_w = OP_ADD;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\t\t3'b010: op_w = OP_LT;\n\t\t\t\t\t\t3'b011: op_w = OP_LTU;\n\t\t\t\t\t\t3'b100: op_w = OP_XOR;\n\t\t\t\t\t\t3'b110: op_w = OP_OR;\n\t\t\t\t\t\tdefault: op_w = OP_AND;\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\tend\n\t\t\tOP_TYPE_BRANCH: begin\n\t\t\t\tcase (instr[14:12])\n\t\t\t\t\t3'b000: op_w = OP_EQ;\n\t\t\t\t\t3'b001: op_w = OP_NE;\n\t\t\t\t\t3'b100: op_w = OP_LT;\n\t\t\t\t\t3'b101: op_w = OP_GE;\n\t\t\t\t\t3'b110: op_w = OP_LTU;\n\t\t\t\t\t3'b111: op_w = OP_GEU;\n\t\t\t\t\tdefault: op_w = OP_GEU;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tOP_TYPE_LDST: begin\n\t\t\t\tcase ({instr[5], instr[14:12]})\n\t\t\t\t\t4'b0000: op_w = OP_LB;\n\t\t\t\t\t4'b0001: op_w = OP_LH;\n\t\t\t\t\t4'b0010: op_w = OP_LW;\n\t\t\t\t\t4'b0100: op_w = OP_LBU;\n\t\t\t\t\t4'b0101: op_w = OP_LHU;\n\t\t\t\t\t4'b1000: op_w = OP_SB;\n\t\t\t\t\t4'b1001: op_w = OP_SH;\n\t\t\t\t\tdefault: op_w = OP_SW;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tOP_TYPE_MDS: begin\n\t\t\t\tcase (instr[14:12])\n\t\t\t\t\t3'b001: op_w = OP_SLL;\n\t\t\t\t\tdefault: op_w = (instr[30])?OP_SRA:OP_SRL;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tOP_TYPE_CSR: begin\n\t\t\t\tcase (instr[13:12])\n\t\t\t\t\t2'b01: op_w = OP_OPA;\n\t\t\t\t\t2'b10: op_w = OP_OR;\n\t\t\t\t\tdefault: op_w = OP_CLR;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tOP_TYPE_SYSTEM: begin\n\t\t\t\tcase (instr[31:28])\n\t\t\t\t\t4'b0000: op_w = (instr[20])?OP_TYPE_EBREAK:OP_TYPE_ECALL;\n\t\t\t\t\tdefault: op_w = OP_TYPE_ERET;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tdefault: op_w = 0;\n\t\tendcase\n\tend\n\tparameter [1:0]\n\t\tSTATE_DECODE = 2'd1,\n\t\tSTATE_REG = (STATE_DECODE + 2'd1);\n\treg [1:0] decode_state;\n\tassign decode_complete = exec_complete;\n\tassign decode_valid = (decode_valid_r && !exec_complete);\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tdecode_state <= STATE_DECODE;\n\t\t\tdecode_valid_r <= 1'b0;\n\t\t\trd_raddr <= 0;\n\t\t\timm_lui <= 0;\n\t\t\top_type <= 0;\n\t\tend else begin\n\t\t\tcase (decode_state)\n\t\t\t\tSTATE_DECODE: begin\n\t\t\t\t\tif (fetch_valid) begin\n\t\t\t\t\t\tdecode_state <= STATE_REG;\n\t\t\t\t\t\timm_lui <= {instr[31:12], 12'h000};\n\t\t\t\t\t\trd_raddr <= rd_raddr_w;\n\t\t\t\t\t\top_type <= op_type_w;\n\t\t\t\t\t\tdecode_valid_r <= 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tdecode_valid_r <= 1'b0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tif (exec_complete) begin\n\t\t\t\t\t\tdecode_state <= STATE_DECODE;\n\t\t\t\t\t\tdecode_valid_r <= 1'b0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_decode",
      "length": 9850,
      "id": 3
    },
    {
      "text": "module fwrisc_exec #(\n\tparameter ENABLE_COMPRESSED=1,\n\tparameter ENABLE_MUL_DIV=1,\n\tparameter ENABLE_DEP=1\n\t)(\n\tinput clock,\n\tinput reset,\n\tinput decode_valid,\n\toutput reg instr_complete,\n\toutput reg trap,\n\toutput reg tret,\n\tinput instr_c,\n\tinput[4:0] op_type,\n\tinput[31:0] op_a,\n\tinput[31:0] op_b,\n\tinput[3:0] op,\n\tinput[31:0] op_c,\n\tinput[5:0] rd,\n\toutput reg[5:0] rd_waddr,\n\toutput reg[31:0] rd_wdata,\n\toutput reg rd_wen,\n\toutput reg[31:0] pc,\n\toutput reg pc_seq,\n\tinput[31:0] mtvec,\n\tinput[31:0] dep_lo,\n\tinput[31:0] dep_hi,\n\toutput[31:0] daddr,\n\toutput dvalid,\n\toutput dwrite,\n\toutput[31:0] dwdata,\n\toutput[3:0] dwstb,\n\tinput[31:0] drdata,\n\tinput dready,\n\tinput irq,\n\tinput meie,\n\tinput mie);\n\tparameter [3:0]\n\t\tOP_ADD = 4'd0,\n\t\tOP_SUB = (OP_ADD+4'd1),\n\t\tOP_AND = (OP_SUB+4'd1),\n\t\tOP_OR = (OP_AND+4'd1),\n\t\tOP_CLR = (OP_OR+4'd1),\n\t\tOP_EQ = (OP_CLR+4'd1),\n\t\tOP_NE = (OP_EQ+4'd1),\n\t\tOP_LT = (OP_NE+4'd1),\n\t\tOP_GE = (OP_LT+4'd1),\n\t\tOP_LTU = (OP_GE+4'd1),\n\t\tOP_GEU = (OP_LTU+4'd1),\n\t\tOP_OPA = (OP_GEU+4'd1),\n\t\tOP_OPB = (OP_OPA+4'd1),\n\t\tOP_XOR = (OP_OPB+4'd1);\n\tparameter [3:0]\n\t\tOP_LB = 4'd0,\n\t\tOP_LH = (OP_LB+4'd1),\n\t\tOP_LW = (OP_LH+4'd1),\n\t\tOP_LBU = (OP_LW+4'd1),\n\t\tOP_LHU = (OP_LBU+4'd1),\n\t\tOP_SB = (OP_LHU + 4'd1),\n\t\tOP_SH = (OP_SB + 4'd1),\n\t\tOP_SW = (OP_SH + 4'd1),\n\t\tOP_NUM_MEM = (OP_SW + 4'd1);\n\tparameter [4:0]\n\t\tOP_TYPE_ARITH = 5'd0,\n\t\tOP_TYPE_BRANCH = (OP_TYPE_ARITH+5'd1),\n\t\tOP_TYPE_LDST = (OP_TYPE_BRANCH+5'd1),\n\t\tOP_TYPE_MDS = (OP_TYPE_LDST+5'd1),\n\t\tOP_TYPE_JUMP = (OP_TYPE_MDS+5'd1),\n\t\tOP_TYPE_SYSTEM = (OP_TYPE_JUMP+5'd1),\n\t\tOP_TYPE_CSR = (OP_TYPE_SYSTEM+5'd1);\n\tparameter [5:0]\n\t\tCSR_BASE_Q0 = 6'h20,\n\t\tCSR_MVENDORID = (CSR_BASE_Q0 + 1'd1),\n\t\tCSR_MARCHID = (CSR_MVENDORID + 1'd1),\n\t\tCSR_MIMPID = (CSR_MARCHID + 1'd1),\n\t\tCSR_MHARTID = (CSR_MIMPID + 1'd1),\n\t\tCSR_BASE_Q1 = 6'h28,\n\t\tCSR_MSTATUS = (CSR_BASE_Q1 + 1'd0),\n\t\tCSR_MISA = (CSR_MSTATUS + 1'd1),\n\t\tCSR_MEDELEG = (CSR_MISA + 1'd1),\n\t\tCSR_MIDELEG = (CSR_MEDELEG + 1'd1),\n\t\tCSR_MIE = (CSR_MIDELEG + 1'd1),\n\t\tCSR_MTVEC = (CSR_MIE + 1'd1),\n\t\tCSR_MCOUNTEREN = (CSR_MTVEC + 1'd1),\n\t\tCSR_BASE_Q2 = 6'h30,\n\t\tCSR_MSCRATCH = (CSR_BASE_Q2 + 1'd0),\n\t\tCSR_MEPC = (CSR_MSCRATCH + 1'd1),\n\t\tCSR_MCAUSE = (CSR_MEPC + 1'd1),\n\t\tCSR_MTVAL = (CSR_MCAUSE + 1'd1),\n\t\tCSR_MIP = (CSR_MTVAL + 1'd1),\n\t\tCSR_BASE_Q3 = 6'h38,\n\t\tCSR_MCYCLE = (CSR_BASE_Q3 + 1'd0),\n\t\tCSR_MCYCLEH = (CSR_MCYCLE + 1'd1),\n\t\tCSR_MINSTRET = (CSR_MCYCLEH + 1'd1),\n\t\tCSR_MINSTRETH = (CSR_MINSTRET + 1'd1),\n\t\tCSR_DEP_LO = (CSR_MINSTRETH + 1'd1),\n\t\tCSR_DEP_HI = (CSR_DEP_LO + 1'd1),\n\t\tCSR_SOFT_RESET = (CSR_DEP_HI + 1'd1);\n\tparameter [3:0]\n\t\tOP_TYPE_ECALL = 1'd0,\n\t\tOP_TYPE_EBREAK = (OP_TYPE_ECALL + 1'd1),\n\t\tOP_TYPE_ERET = (OP_TYPE_EBREAK + 1'd1);\n\tparameter [3:0]\n\t\tSTATE_EXECUTE = 4'd0,\n\t\tSTATE_BRANCH_TAKEN = (STATE_EXECUTE + 4'd1),\n\t\tSTATE_JUMP = (STATE_BRANCH_TAKEN + 4'd1),\n\t\tSTATE_CSR = (STATE_JUMP + 4'd1),\n\t\tSTATE_MDS_COMPLETE = (STATE_CSR + 4'd1),\n\t\tSTATE_LDST_COMPLETE = (STATE_MDS_COMPLETE + 4'd1),\n\t\tSTATE_EXCEPTION_1 = (STATE_LDST_COMPLETE + 4'd1),\n\t\tSTATE_EXCEPTION_2 = (STATE_EXCEPTION_1 + 4'd1),\n\t\tSTATE_EXCEPTION_3 = (STATE_EXCEPTION_2 + 4'd1);\n\treg [3:0] exec_state;\n\treg[31:0] pc_next;\n\treg pc_seq_next;\n\twire mds_in_valid = (\n\t\t(op_type == OP_TYPE_MDS && exec_state == STATE_EXECUTE)\n\t\t&& decode_valid\n\t);\n\twire mds_out_valid;\n\twire[31:0] mds_out;\n\twire mem_req_valid;\n\twire[31:0] mem_req_addr;\n\twire mem_ack_valid;\n\twire[31:0] mem_ack_data;\n\treg[2:0] next_pc_seq_incr;\n\treg mcause_int;\n\treg[3:0] mcause;\n\twire[31:0] next_pc_seq = pc + next_pc_seq_incr;\n\treg[31:0] mtval = 0;\n\twire [31:0] alu_out;\n\twire dep_violation;\n\tgenerate\n\tif (ENABLE_DEP) begin\n\t\tassign dep_violation = (\n\t\t\tdep_lo[0] && dep_hi[0]\n\t\t\t&& (exec_state == STATE_JUMP)\n\t\t\t&& !(alu_out[31:3] >= dep_lo[31:3] && alu_out[31:3] <= dep_hi[31:3])\n\t\t);\n\tend else begin\n\t\tassign dep_violation = 0;\n\tend\n\tendgenerate\n\twire ei_req = (irq && meie && mie);\n\twire jump_target_misaligned;\n\tgenerate\n\tif (!ENABLE_COMPRESSED) begin\n\t\tassign jump_target_misaligned = (\n\t\t\t(exec_state == STATE_JUMP || exec_state == STATE_BRANCH_TAKEN)\n\t\t\t&& alu_out[1]\n\t\t);\n\tend else begin\n\t\tassign jump_target_misaligned = 0;\n\tend\n\tendgenerate\n\treg ldst_addr_misaligned;\n\talways @* begin\n\t\tif (exec_state == STATE_EXECUTE && op_type == OP_TYPE_LDST) begin\n\t\t\tcase (op)\n\t\t\t\tOP_LH, OP_LHU, OP_SH: ldst_addr_misaligned = alu_out[0];\n\t\t\t\tOP_LW, OP_SW: ldst_addr_misaligned = |alu_out[1:0];\n\t\t\t\tdefault: ldst_addr_misaligned = 0;\n\t\t\tendcase\n\t\tend else begin\n\t\t\tldst_addr_misaligned = 0;\n\t\tend\n\tend\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tmtval <= 0;\n\t\tend else begin\n\t\t\tif (jump_target_misaligned || dep_violation || ldst_addr_misaligned) begin\n\t\t\t\tcase (op_type)\n\t\t\t\t\tOP_TYPE_JUMP: mtval <= {alu_out[31:1], 1'b0};\n\t\t\t\t\tdefault: mtval <= alu_out;\n\t\t\t\tendcase\n\t\t\tend\n\t\tend\n\tend\n\talways @* begin\n\t\tif (exec_state == STATE_BRANCH_TAKEN || exec_state == STATE_JUMP) begin\n\t\t\tnext_pc_seq_incr = 0;\n\t\tend else begin\n\t\t\tnext_pc_seq_incr = (instr_c)?2:4;\n\t\tend\n\tend\n\twire branch_taken = ((op_type == OP_TYPE_BRANCH && alu_out[0]) || op_type == OP_TYPE_JUMP);\n\talways @* begin\n\t\tif (exec_state == STATE_BRANCH_TAKEN || exec_state == STATE_JUMP) begin\n\t\t\tpc_next = {alu_out[31:1], 1'b0};\n\t\t\tpc_seq_next = 0;\n\t\tend else begin\n\t\t\tpc_next = next_pc_seq;\n\t\t\tpc_seq_next = 1;\n\t\tend\n\tend\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\texec_state <= STATE_EXECUTE;\n\t\t\tinstr_complete <= 1'b0;\n\t\t\ttrap <= 1'b0;\n\t\t\ttret <= 1'b0;\n\t\t\tpc <= 'h8000_0000;\n\t\t\tpc_seq <= 1;\n\t\t\tmcause <= 4'b0;\n\t\t\tmcause_int <= 1'b0;\n\t\tend else begin\n\t\t\tcase (exec_state)\n\t\t\t\tSTATE_EXECUTE: begin\n\t\t\t\t\tif (decode_valid) begin\n\t\t\t\t\t\tif (ei_req) begin\n\t\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\t\t\tmcause <= 4'd11;\n\t\t\t\t\t\t\tmcause_int <= 1'b1;\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tcase (op_type)\n\t\t\t\t\t\t\t\tOP_TYPE_ARITH: begin\n\t\t\t\t\t\t\t\t\tpc <= pc_next;\n\t\t\t\t\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_TYPE_BRANCH: begin\n\t\t\t\t\t\t\t\t\tif (alu_out[0]) begin\n\t\t\t\t\t\t\t\t\t\texec_state <= STATE_BRANCH_TAKEN;\n\t\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\t\tpc <= pc_next;\n\t\t\t\t\t\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_TYPE_LDST: begin\n\t\t\t\t\t\t\t\t\tif (ldst_addr_misaligned) begin\n\t\t\t\t\t\t\t\t\t\tif (op == OP_SB || op == OP_SH || op == OP_SW) begin\n\t\t\t\t\t\t\t\t\t\t\tmcause <= 6;\n\t\t\t\t\t\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\t\t\tmcause <= 4;\n\t\t\t\t\t\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\t\texec_state <= STATE_LDST_COMPLETE;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_TYPE_MDS: begin\n\t\t\t\t\t\t\t\t\texec_state <= STATE_MDS_COMPLETE;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_TYPE_JUMP: begin\n\t\t\t\t\t\t\t\t\texec_state <= STATE_JUMP;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_TYPE_SYSTEM: begin\n\t\t\t\t\t\t\t\t\tif (op == OP_TYPE_ERET) begin\n\t\t\t\t\t\t\t\t\t\tinstr_complete <= 1'b1;\n\t\t\t\t\t\t\t\t\t\ttret <= 1'b1;\n\t\t\t\t\t\t\t\t\t\tpc <= op_a;\n\t\t\t\t\t\t\t\t\t\tpc_seq <= 0;\n\t\t\t\t\t\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\t\tmcause <= (op == OP_TYPE_EBREAK)?3:11;\n\t\t\t\t\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\t\t\texec_state <= STATE_CSR;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\tend\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tinstr_complete <= 1'b0;\n\t\t\t\t\t\ttrap <= 1'b0;\n\t\t\t\t\t\ttret <= 1'b0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_CSR: begin\n\t\t\t\t\tpc <= pc_next;\n\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\tend\n\t\t\t\tSTATE_JUMP: begin\n\t\t\t\t\tcase ({dep_violation, jump_target_misaligned})\n\t\t\t\t\t\t2'b00: begin\n\t\t\t\t\t\t\tpc <= {alu_out[31:1], 1'b0};\n\t\t\t\t\t\t\tpc_seq <= 0;\n\t\t\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\t\tend\n\t\t\t\t\t\t2'b01: begin\n\t\t\t\t\t\t\tmcause <= 0;\n\t\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\t\tend\n\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\tmcause <= 1;\n\t\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\t\tend\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\t\tSTATE_BRANCH_TAKEN: begin\n\t\t\t\t\tif (jump_target_misaligned) begin\n\t\t\t\t\t\tmcause <= 0;\n\t\t\t\t\t\tmcause_int <= 1'b0;\n\t\t\t\t\t\texec_state <= STATE_EXCEPTION_1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tpc <= alu_out;\n\t\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_MDS_COMPLETE: begin\n\t\t\t\t\tif (mds_out_valid) begin\n\t\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\t\tpc <= pc_next;\n\t\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_LDST_COMPLETE: begin\n\t\t\t\t\tif (mem_ack_valid) begin\n\t\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\t\t\tpc <= pc_next;\n\t\t\t\t\t\tpc_seq <= pc_seq_next;\n\t\t\t\t\t\tinstr_complete <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_EXCEPTION_1: begin\n\t\t\t\t\texec_state <= STATE_EXCEPTION_2;\n\t\t\t\tend\n\t\t\t\tSTATE_EXCEPTION_2: begin\n\t\t\t\t\texec_state <= STATE_EXCEPTION_3;\n\t\t\t\tend\n\t\t\t\tSTATE_EXCEPTION_3: begin\n\t\t\t\t\tpc <= mtvec;\n\t\t\t\t\tpc_seq <= 1'b0;\n\t\t\t\t\tinstr_complete <= 1'b1;\n\t\t\t\t\ttrap <= 1'b1;\n\t\t\t\t\texec_state <= STATE_EXECUTE;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\n\twire alu_op_a_sel_pc = (\n\t\t(exec_state == STATE_BRANCH_TAKEN)\n\t\t|| (exec_state == STATE_EXECUTE && op_type == OP_TYPE_JUMP)\n\t);\n\twire alu_op_b_sel_c = (\n\t\t(exec_state == STATE_BRANCH_TAKEN)\n\t\t|| (exec_state == STATE_JUMP)\n\t\t|| (exec_state == STATE_EXECUTE && op_type == OP_TYPE_LDST)\n\t);\n\twire alu_op_sel_add = (\n\t\t(exec_state == STATE_EXECUTE && op_type == OP_TYPE_LDST)\n\t\t|| (exec_state == STATE_BRANCH_TAKEN)\n\t\t|| (exec_state == STATE_JUMP)\n\t);\n\twire alu_op_sel_opb = (\n\t\t(exec_state == STATE_CSR)\n\t);\n\twire alu_op_sel_opa = (\n\t\t(exec_state == STATE_EXECUTE && op_type == OP_TYPE_JUMP)\n\t\t|| (exec_state == STATE_JUMP)\n\t);\n\twire [31:0] alu_op_a = (alu_op_a_sel_pc)?next_pc_seq:op_a;\n\twire [31:0] alu_op_b = (alu_op_b_sel_c)?op_c:op_b;\n\treg [3:0] alu_op;\n\talways @* begin\n\t\tcase ({alu_op_sel_add,alu_op_sel_opb,alu_op_sel_opa})\n\t\t\t3'b100: alu_op = OP_ADD;\n\t\t\t3'b010: alu_op = OP_OPB;\n\t\t\t3'b001: alu_op = OP_OPA;\n\t\t\tdefault: alu_op = op;\n\t\tendcase\n\tend\n\talways @* begin\n\t\trd_wen = (decode_valid && !instr_complete &&\n\t\t\t\t(\n\t\t\t\t\t(exec_state == STATE_EXECUTE) &&\n\t\t\t\t\t\t(op_type == OP_TYPE_ARITH || op_type == OP_TYPE_JUMP\n\t\t\t\t\t\t\t|| op_type == OP_TYPE_CSR)\n\t\t\t\t\t|| (exec_state == STATE_CSR)\n\t\t\t\t\t|| (exec_state == STATE_LDST_COMPLETE\n\t\t\t\t\t\t&& (op == OP_LB || op == OP_LH || op == OP_LW\n\t\t\t\t\t\t\t|| op == OP_LBU || op == OP_LHU) && mem_ack_valid)\n\t\t\t\t\t|| (exec_state == STATE_MDS_COMPLETE && mds_out_valid)\n\t\t\t\t\t|| (exec_state == STATE_EXCEPTION_1 || exec_state == STATE_EXCEPTION_2 || exec_state == STATE_EXCEPTION_3)\n\t\t\t\t)\n\t\t);\n\tend\n\talways @* begin\n\t\tcase (exec_state)\n\t\t\tSTATE_EXCEPTION_1: rd_wdata = pc;\n\t\t\tSTATE_EXCEPTION_2: rd_wdata = mtval;\n\t\t\tSTATE_EXCEPTION_3: rd_wdata = {mcause_int, 27'b0, mcause};\n\t\t\tSTATE_MDS_COMPLETE: rd_wdata = mds_out;\n\t\t\tSTATE_LDST_COMPLETE: rd_wdata = mem_ack_data;\n\t\t\tdefault: rd_wdata = alu_out;\n\t\tendcase\n\t\tcase (exec_state)\n\t\t\tSTATE_EXECUTE: rd_waddr = (op_type == OP_TYPE_CSR)?op_c[5:0]:rd;\n\t\t\tSTATE_EXCEPTION_1: rd_waddr = CSR_MEPC;\n\t\t\tSTATE_EXCEPTION_2: rd_waddr = CSR_MTVAL;\n\t\t\tSTATE_EXCEPTION_3: rd_waddr = CSR_MCAUSE;\n\t\t\tdefault: rd_waddr = rd;\n\t\tendcase\n\tend\n\tfwrisc_alu u_alu (\n\t\t.clock (clock),\n\t\t.reset (reset),\n\t\t.op_a (alu_op_a),\n\t\t.op_b (alu_op_b),\n\t\t.op (alu_op),\n\t\t.out (alu_out));\n\tfwrisc_mul_div_shift #(\n\t\t.ENABLE_MUL_DIV (ENABLE_MUL_DIV)\n\t\t) u_mds (\n\t\t.clock (clock),\n\t\t.reset (reset),\n\t\t.in_a (op_a),\n\t\t.in_b (op_b),\n\t\t.op (op[3:0]),\n\t\t.in_valid (mds_in_valid),\n\t\t.out (mds_out),\n\t\t.out_valid (mds_out_valid));\n\tassign mem_req_addr = alu_out;\n\tassign mem_req_valid = (\n\t\texec_state == STATE_EXECUTE\n\t\t&& op_type == OP_TYPE_LDST\n\t\t&& decode_valid && !ldst_addr_misaligned);\n\tfwrisc_mem u_mem (\n\t\t.clock (clock),\n\t\t.reset (reset),\n\t\t.req_valid (mem_req_valid),\n\t\t.req_addr (mem_req_addr),\n\t\t.req_op (op[3:0]),\n\t\t.req_data (op_b),\n\t\t.ack_valid (mem_ack_valid),\n\t\t.ack_data (mem_ack_data),\n\t\t.dvalid (dvalid),\n\t\t.daddr (daddr),\n\t\t.dwdata (dwdata),\n\t\t.dwstb (dwstb),\n\t\t.dwrite (dwrite),\n\t\t.drdata (drdata),\n\t\t.dready (dready));\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_exec",
      "length": 11866,
      "id": 4
    },
    {
      "text": "module fwrisc_fetch #(\n\tparameter ENABLE_COMPRESSED=1\n\t)(\n\tinput clock,\n\tinput reset,\n\tinput[31:0] next_pc,\n\tinput next_pc_seq,\n\toutput reg[31:0] iaddr,\n\tinput[31:0] idata,\n\toutput ivalid,\n\tinput iready,\n\toutput fetch_valid,\n\tinput decode_complete,\n\toutput reg[31:0] instr,\n\toutput reg instr_c);\n\treg[2:0] state;\n\treg[15:0] instr_cache;\n\twire instr_cache_c = (&instr_cache[1:0] != 1);\n\treg instr_cache_valid;\n\twire instr_c_lo = (&idata[1:0] != 1);\n\twire instr_c_hi = (&idata[17:16] != 1);\n\twire instr_c_next = (next_pc[1])?instr_c_hi:instr_c_lo;\n\tparameter [2:0]\n\t\tSTATE_FETCH1 = 3'd0,\n\t\tSTATE_FETCH2 = (STATE_FETCH1 + 3'd1),\n\t\tSTATE_WAIT_DECODE = (STATE_FETCH2 + 3'd1);\n\treg fetch_valid_r;\n\tassign fetch_valid = (fetch_valid_r && !decode_complete);\n\treg ivalid_r;\n\tassign ivalid = (ivalid_r);\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tstate <= STATE_FETCH1;\n\t\t\tinstr_cache_valid <= 0;\n\t\t\tinstr_cache <= {16{1'b0}};\n\t\t\tfetch_valid_r <= 0;\n\t\t\tivalid_r <= 0;\n\t\t\tinstr_c <= 0;\n\t\t\tinstr <= {32{1'b0}};\n\t\tend else begin\n\t\t\tcase (state)\n\t\t\t\tdefault: begin\n\t\t\t\t\tiaddr <= {next_pc[31:2], 2'b0};\n\t\t\t\t\tif (iready && ivalid_r) begin\n\t\t\t\t\t\tinstr_c <= instr_c_next;\n\t\t\t\t\t\tcase ({next_pc[1], instr_c_next})\n\t\t\t\t\t\t\t2'b00: begin\n\t\t\t\t\t\t\t\tinstr <= idata;\n\t\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\t\tfetch_valid_r <= 1;\n\t\t\t\t\t\t\t\tivalid_r <= 0;\n\t\t\t\t\t\t\t\tstate <= STATE_WAIT_DECODE;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t2'b01: begin\n\t\t\t\t\t\t\t\tinstr <= idata[15:0];\n\t\t\t\t\t\t\t\tinstr_cache <= idata[31:16];\n\t\t\t\t\t\t\t\tinstr_cache_valid <= 1;\n\t\t\t\t\t\t\t\tfetch_valid_r <= 1;\n\t\t\t\t\t\t\t\tivalid_r <= 0;\n\t\t\t\t\t\t\t\tstate <= STATE_WAIT_DECODE;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t2'b10: begin\n\t\t\t\t\t\t\t\tinstr[15:0] <= idata[31:16];\n\t\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\t\tivalid_r <= 1;\n\t\t\t\t\t\t\t\tstate <= STATE_FETCH2;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t2'b11: begin\n\t\t\t\t\t\t\t\tinstr[15:0] <= idata[31:16];\n\t\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\t\tivalid_r <= 0;\n\t\t\t\t\t\t\t\tstate <= STATE_WAIT_DECODE;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tivalid_r <= 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_WAIT_DECODE: begin\n\t\t\t\t\tif (decode_complete) begin\n\t\t\t\t\t\tfetch_valid_r <= 0;\n\t\t\t\t\t\tstate <= STATE_FETCH1;\n`ifdef UNDEFINED\n\t\t\t\t\t\tif (!next_pc_seq) begin\n\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\tstate <= STATE_FETCH1;\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tcase ({instr_c, instr_cache_valid, instr_cache_c})\n\t\t\t\t\t\t\t\t3'b111: begin\n\t\t\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\t\t\tinstr <= instr_cache;\n\t\t\t\t\t\t\t\t\tinstr_c <= 1;\n\t\t\t\t\t\t\t\t\tstate <= 3'b001;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\t\t\tinstr_cache_valid <= 0;\n\t\t\t\t\t\t\t\t\tstate <= STATE_FETCH1;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\tend\n`endif\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tSTATE_FETCH2: begin\n\t\t\t\t\tiaddr <= {next_pc[31:2]+1'd1, 2'b0};\n\t\t\t\t\tif (iready) begin\n\t\t\t\t\t\tivalid_r <= 0;\n\t\t\t\t\t\tinstr[31:16] <= idata[15:0];\n\t\t\t\t\t\tinstr_cache <= idata[31:16];\n\t\t\t\t\t\tinstr_cache_valid <= 1;\n\t\t\t\t\t\tfetch_valid_r <= 1;\n\t\t\t\t\t\tstate <= STATE_WAIT_DECODE;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_fetch",
      "length": 2897,
      "id": 5
    },
    {
      "text": "module fwrisc_mem (\n\tinput clock,\n\tinput reset,\n\tinput req_valid,\n\tinput[31:0] req_addr,\n\tinput[3:0] req_op,\n\tinput[31:0] req_data,\n\toutput reg ack_valid,\n\toutput reg[31:0] ack_data,\n\toutput reg dvalid,\n\toutput reg[31:0] daddr,\n\toutput reg[31:0] dwdata,\n\toutput reg[3:0] dwstb,\n\toutput reg dwrite,\n\tinput[31:0] drdata,\n\tinput dready);\n\tparameter [3:0]\n\t\tOP_LB = 4'd0,\n\t\tOP_LH = (OP_LB+4'd1),\n\t\tOP_LW = (OP_LH+4'd1),\n\t\tOP_LBU = (OP_LW+4'd1),\n\t\tOP_LHU = (OP_LBU+4'd1),\n\t\tOP_SB = (OP_LHU + 4'd1),\n\t\tOP_SH = (OP_SB + 4'd1),\n\t\tOP_SW = (OP_SH + 4'd1),\n\t\tOP_NUM_MEM = (OP_SW + 4'd1);\n\tparameter[1:0]\n\t\tSTATE_WAIT_REQ = 2'd0,\n\t\tSTATE_WAIT_RSP = (STATE_WAIT_REQ + 2'd1);\n\treg[1:0] mem_state;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tack_valid <= 0;\n\t\t\tack_data <= {32{1'b0}};\n\t\t\tmem_state <= 0;\n\t\t\tdvalid <= 0;\n\t\t\tdaddr <= 0;\n\t\t\tdwdata <= 0;\n\t\t\tdwstb <= 0;\n\t\t\tdwrite <= 0;\n\t\tend else begin\n\t\t\tcase (mem_state)\n\t\t\t\tSTATE_WAIT_REQ: begin\n\t\t\t\t\tack_valid <= 0;\n\t\t\t\t\tif (req_valid && !ack_valid) begin\n\t\t\t\t\t\tdvalid <= 1;\n\t\t\t\t\t\tdaddr <= req_addr;\n\t\t\t\t\t\tmem_state <= STATE_WAIT_RSP;\n\t\t\t\t\t\tdwrite <= (req_op == OP_SB || req_op == OP_SH || req_op == OP_SW);\n\t\t\t\t\t\tcase (req_op)\n\t\t\t\t\t\t\tOP_SB: begin\n\t\t\t\t\t\t\t\tcase (req_addr[1:0])\n\t\t\t\t\t\t\t\t\t2'b00: dwstb <= 4'b0001;\n\t\t\t\t\t\t\t\t\t2'b01: dwstb <= 4'b0010;\n\t\t\t\t\t\t\t\t\t2'b10: dwstb <= 4'b0100;\n\t\t\t\t\t\t\t\t\t2'b11: dwstb <= 4'b1000;\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\t\tdwdata <= {4{req_data[7:0]}};\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tOP_SH: begin\n\t\t\t\t\t\t\t\tcase (req_addr[1])\n\t\t\t\t\t\t\t\t\t0: dwstb <= 4'b0011;\n\t\t\t\t\t\t\t\t\t1: dwstb <= 4'b1100;\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\t\tdwdata <= {2{req_data[15:0]}};\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tOP_SW: begin\n\t\t\t\t\t\t\t\tdwstb <= 4'b1111;\n\t\t\t\t\t\t\t\tdwdata <= req_data;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\t\tdwstb <= 4'b0000;\n\t\t\t\t\t\t\t\tdwdata <= 32'b0;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tif (dready) begin\n\t\t\t\t\t\tack_valid <= 1;\n\t\t\t\t\t\tdvalid <= 0;\n\t\t\t\t\t\tdwrite <= 0;\n\t\t\t\t\t\tdwstb <= 0;\n\t\t\t\t\t\tcase (req_op)\n\t\t\t\t\t\t\tOP_LB: begin\n\t\t\t\t\t\t\t\tcase (daddr[1:0])\n\t\t\t\t\t\t\t\t\t2'b00: ack_data <= $signed(drdata[7:0]);\n\t\t\t\t\t\t\t\t\t2'b01: ack_data <= $signed(drdata[15:8]);\n\t\t\t\t\t\t\t\t\t2'b10: ack_data <= $signed(drdata[23:16]);\n\t\t\t\t\t\t\t\t\t2'b11: ack_data <= $signed(drdata[31:24]);\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tOP_LBU: begin\n\t\t\t\t\t\t\t\tcase (daddr[1:0])\n\t\t\t\t\t\t\t\t\t2'b00: ack_data <= drdata[7:0];\n\t\t\t\t\t\t\t\t\t2'b01: ack_data <= drdata[15:8];\n\t\t\t\t\t\t\t\t\t2'b10: ack_data <= drdata[23:16];\n\t\t\t\t\t\t\t\t\t2'b11: ack_data <= drdata[31:24];\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tOP_LH: begin\n\t\t\t\t\t\t\t\tcase (daddr[1])\n\t\t\t\t\t\t\t\t\t0: ack_data <= $signed(drdata[15:0]);\n\t\t\t\t\t\t\t\t\t1: ack_data <= $signed(drdata[31:16]);\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tOP_LHU: begin\n\t\t\t\t\t\t\t\tcase (daddr[1])\n\t\t\t\t\t\t\t\t\t0: ack_data <= drdata[15:0];\n\t\t\t\t\t\t\t\t\t1: ack_data <= drdata[31:16];\n\t\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tdefault: begin\n\t\t\t\t\t\t\t\tack_data <= drdata;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tmem_state <= STATE_WAIT_REQ;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_mem",
      "length": 2929,
      "id": 6
    },
    {
      "text": "module fwrisc_mul_div_shift #(\n\tparameter ENABLE_MUL_DIV=1,\n\tparameter ENABLE_MUL=ENABLE_MUL_DIV,\n\tparameter ENABLE_DIV=ENABLE_MUL_DIV,\n\tparameter SINGLE_CYCLE_SHIFT=0\n\t)(\n\tinput clock,\n\tinput reset,\n\tinput[31:0] in_a,\n\tinput[31:0] in_b,\n\tinput[3:0] op,\n\tinput in_valid,\n\toutput reg[31:0] out,\n\toutput reg out_valid);\n\tparameter [3:0]\n\t\tOP_SLL = 4'd0,\n\t\tOP_SRL = (OP_SLL + 4'd1),\n\t\tOP_SRA = (OP_SRL + 4'd1),\n\t\tOP_MUL = (OP_SRA + 4'd1),\n\t\tOP_MULH = (OP_MUL + 4'd1),\n\t\tOP_MULS = (OP_MULH + 4'd1),\n\t\tOP_MULSH = (OP_MULS + 4'd1),\n\t\tOP_DIV = (OP_MULSH + 4'd1),\n\t\tOP_REM = (OP_DIV + 4'd1),\n\t\tOP_NUM_MDS = (OP_REM + 4'd1);\n\treg[3:0] op_r;\n\treg[4:0] shift_amt_r;\n\treg working;\n\treg[63:0] mul_res;\n\treg[31:0] mul_tmp1;\n\treg[31:0] mul_tmp2;\n\treg[62:0] div_divisor;\n\treg[31:0] div_dividend;\n\treg[31:0] div_quotient;\n\treg[31:0] div_msk;\n\treg div_sign;\n\twire mul_tmp2_zero = (|mul_tmp2 == 0);\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tout <= 32'b0;\n\t\t\tout_valid <= 0;\n\t\t\tworking <= 0;\n\t\t\top_r <= 0;\n\t\tend else begin\n\t\t\tif (in_valid) begin\n\t\t\t\top_r <= op;\n\t\t\t\tworking <= 1;\n\t\t\t\tcase (op)\n\t\t\t\t\tOP_SLL, OP_SRL, OP_SRA: begin\n\t\t\t\t\t\tif (SINGLE_CYCLE_SHIFT) begin\n\t\t\t\t\t\t\tshift_amt_r <= 0;\n\t\t\t\t\t\t\tcase (op_r)\n\t\t\t\t\t\t\t\tOP_SLL: begin\n\t\t\t\t\t\t\t\t\tif (|in_b[4:0]) begin\n\t\t\t\t\t\t\t\t\t\tout <= (out << in_b[4:0]);\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_SRL: begin\n\t\t\t\t\t\t\t\t\tif (|in_b[4:0]) begin\n\t\t\t\t\t\t\t\t\t\tout <= (out >> in_b[4:0]);\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tOP_SRA: begin\n\t\t\t\t\t\t\t\t\tif (|in_b[4:0]) begin\n\t\t\t\t\t\t\t\t\t\tout <= (out >>> in_b[4:0]);\n\t\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tendcase\n\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\tshift_amt_r <= in_b[4:0];\n\t\t\t\t\t\t\tout <= in_a;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_MUL, OP_MULH: begin\n\t\t\t\t\t\tif (ENABLE_MUL) begin\n\t\t\t\t\t\t\tmul_res <= 64'b0;\n\t\t\t\t\t\t\tmul_tmp1 <= in_a;\n\t\t\t\t\t\t\tmul_tmp2 <= in_b;\n\t\t\t\t\t\t\tshift_amt_r <= 5'd31;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_MULS, OP_MULSH: begin\n\t\t\t\t\t\tif (ENABLE_MUL) begin\n\t\t\t\t\t\t\tmul_res <= 64'b0;\n\t\t\t\t\t\t\tmul_tmp1 <= $signed(in_a);\n\t\t\t\t\t\t\tmul_tmp2 <= $signed(in_b);\n\t\t\t\t\t\t\tshift_amt_r <= 5'd31;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_DIV, OP_REM: begin\n\t\t\t\t\t\tif (ENABLE_DIV) begin\n\t\t\t\t\t\t\tif (in_a[31]) begin\n\t\t\t\t\t\t\t\tdiv_dividend <= -in_a;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tdiv_dividend <= in_a;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (in_b[31]) begin\n\t\t\t\t\t\t\t\tdiv_divisor <= (-in_b) << 31;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tdiv_divisor <= in_b << 31;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tshift_amt_r <= 5'd31;\n\t\t\t\t\t\t\tdiv_msk <= 'h8000_0000;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\t\tif (op == OP_DIV) begin\n\t\t\t\t\tdiv_sign <= (in_a[31] != in_a[31]);\n\t\t\t\tend else begin\n\t\t\t\t\tdiv_sign <= in_a[31];\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (working) begin\n\t\t\t\tcase (op_r)\n\t\t\t\t\tOP_SLL: begin\n\t\t\t\t\t\tif (|shift_amt_r) begin\n\t\t\t\t\t\t\tout <= (out << 1);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_SRL: begin\n\t\t\t\t\t\tif (|shift_amt_r) begin\n\t\t\t\t\t\t\tout <= (out >> 1);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_SRA: begin\n\t\t\t\t\t\tif (|shift_amt_r) begin\n\t\t\t\t\t\t\tout <= ($signed(out) >>> 1);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_MUL, OP_MULS, OP_MULH, OP_MULSH: begin\n\t\t\t\t\t\tif (ENABLE_MUL) begin\n\t\t\t\t\t\t\tif (mul_tmp1[0]) begin\n\t\t\t\t\t\t\t\tmul_res <= (mul_res + mul_tmp2);\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tmul_tmp2 <= (mul_tmp2 << 1);\n\t\t\t\t\t\t\tmul_tmp1 <= (mul_tmp1 >> 1);\n\t\t\t\t\t\t\tif (op_r == OP_MUL || op_r == OP_MULS) begin\n\t\t\t\t\t\t\t\tout <= mul_res[31:0];\n\t\t\t\t\t\t\tend else begin // mulh/mulsh\n\t\t\t\t\t\t\t\tout <= mul_res[63:32];\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tOP_DIV, OP_REM: begin\n\t\t\t\t\t\tif (ENABLE_DIV) begin\n\t\t\t\t\t\t\tif (div_divisor <= div_dividend) begin\n\t\t\t\t\t\t\t\tdiv_dividend <= div_dividend - div_divisor;\n\t\t\t\t\t\t\t\tdiv_quotient <= div_quotient | div_msk;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tdiv_divisor <= div_divisor >> 1;\n\t\t\t\t\t\t\tdiv_msk <= div_msk >> 1;\n\t\t\t\t\t\t\tif (op == OP_DIV) begin\n\t\t\t\t\t\t\t\tout <= (div_sign)?-div_quotient:div_quotient;\n\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\tout <= (div_sign)?-div_dividend:div_dividend;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\t\tif (|shift_amt_r == 0) begin\n\t\t\t\t\tworking <= 1'b0;\n\t\t\t\t\tout_valid <= 1'b1;\n\t\t\t\tend else begin\n\t\t\t\t\tshift_amt_r <= shift_amt_r - 1;\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tout_valid <= 0;\n\t\t\tend\n\t\tend\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_mul_div_shift",
      "length": 3995,
      "id": 7
    },
    {
      "text": "module fwrisc_regfile #(\n\tparameter ENABLE_COUNTERS=1,\n\tparameter ENABLE_DEP=1,\n\tparameter[31:0] VENDORID=0,\n\tparameter[31:0] ARCHID=0,\n\tparameter[31:0] IMPID=0,\n\tparameter[31:0] HARTID=0,\n\tparameter[31:0] ISA=0\n\t)(\n\tinput clock,\n\tinput reset,\n\toutput soft_reset_req,\n\tinput instr_complete,\n\tinput trap,\n\tinput tret,\n\tinput irq,\n\tinput[5:0] ra_raddr,\n\toutput reg[31:0] ra_rdata,\n\tinput[5:0] rb_raddr,\n\toutput reg[31:0] rb_rdata,\n\tinput[5:0] rd_waddr,\n\tinput[31:0] rd_wdata,\n\tinput rd_wen,\n\toutput[31:0] dep_lo,\n\toutput[31:0] dep_hi,\n\toutput[31:0] mtvec,\n\toutput reg meie,\n\toutput reg mie);\n\tparameter [5:0]\n\t\tCSR_BASE_Q0 = 6'h20,\n\t\tCSR_MVENDORID = (CSR_BASE_Q0 + 1'd1),\n\t\tCSR_MARCHID = (CSR_MVENDORID + 1'd1),\n\t\tCSR_MIMPID = (CSR_MARCHID + 1'd1),\n\t\tCSR_MHARTID = (CSR_MIMPID + 1'd1),\n\t\tCSR_BASE_Q1 = 6'h28,\n\t\tCSR_MSTATUS = (CSR_BASE_Q1 + 1'd0),\n\t\tCSR_MISA = (CSR_MSTATUS + 1'd1),\n\t\tCSR_MEDELEG = (CSR_MISA + 1'd1),\n\t\tCSR_MIDELEG = (CSR_MEDELEG + 1'd1),\n\t\tCSR_MIE = (CSR_MIDELEG + 1'd1),\n\t\tCSR_MTVEC = (CSR_MIE + 1'd1),\n\t\tCSR_MCOUNTEREN = (CSR_MTVEC + 1'd1),\n\t\tCSR_BASE_Q2 = 6'h30,\n\t\tCSR_MSCRATCH = (CSR_BASE_Q2 + 1'd0),\n\t\tCSR_MEPC = (CSR_MSCRATCH + 1'd1),\n\t\tCSR_MCAUSE = (CSR_MEPC + 1'd1),\n\t\tCSR_MTVAL = (CSR_MCAUSE + 1'd1),\n\t\tCSR_MIP = (CSR_MTVAL + 1'd1),\n\t\tCSR_BASE_Q3 = 6'h38,\n\t\tCSR_MCYCLE = (CSR_BASE_Q3 + 1'd0),\n\t\tCSR_MCYCLEH = (CSR_MCYCLE + 1'd1),\n\t\tCSR_MINSTRET = (CSR_MCYCLEH + 1'd1),\n\t\tCSR_MINSTRETH = (CSR_MINSTRET + 1'd1),\n\t\tCSR_DEP_LO = (CSR_MINSTRETH + 1'd1),\n\t\tCSR_DEP_HI = (CSR_DEP_LO + 1'd1),\n\t\tCSR_SOFT_RESET = (CSR_DEP_HI + 1'd1);\n\treg[63:0] cycle_count;\n\treg[63:0] instr_count;\n\treg[31:0] dep_lo_r;\n\treg[31:0] dep_hi_r;\n\treg[31:0] mtvec_r;\n\treg[31:0] mscratch;\n\treg[31:0] regs['h3f:0];\n\tgenerate\n\tif (ENABLE_DEP) begin\n\t\tassign dep_lo = dep_lo_r;\n\t\tassign dep_hi = dep_hi_r;\n\tend else begin\n\t\tassign dep_lo = 0;\n\t\tassign dep_hi = 0;\n\tend\n\tendgenerate\n\tassign mtvec = mtvec_r;\n`ifdef FORMAL\n\tinitial regs[0] = 0;\n`else\n\t`ifdef FWRISC_SOFT_CORE\n\tinitial begin\n\t\t$readmemh(\"regs.hex\", regs);\n\tend\n\t`endif\n`endif\n\treg mpie;\n\tassign soft_reset_req = (rd_wen && rd_waddr == CSR_SOFT_RESET);\n\tinteger reg_i;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tcycle_count <= 0;\n\t\t\tinstr_count <= 0;\n\t\t\tdep_lo_r <= 0;\n\t\t\tdep_hi_r <= 0;\n\t\t\tmtvec_r <= 0;\n\t\t\tmscratch <= {32{1'b0}};\n\t\t\tmtvec_r <= {32{1'b0}};\n\t\t\tmeie <= 1'b1;\n\t\t\tmie <= 1'b1;\n\t\t\tmpie <= 1'b0;\n\t\t\t`ifndef FWRISC_SOFT_CORE\n\t\t\tfor (reg_i=0; reg_i<'h40; reg_i=reg_i+1) begin\n\t\t\t\tregs[reg_i] <= {32{1'b0}};\n\t\t\tend\n\t\t\t`endif\n\t\tend else begin\n\t\t\tcase ({rd_wen, rd_waddr})\n\t\t\t\t{1'b1, CSR_MCYCLE}: cycle_count <= {cycle_count[63:32], rd_wdata};\n\t\t\t\t{1'b1, CSR_MCYCLEH}: cycle_count <= {rd_wdata, cycle_count[31:0]};\n\t\t\t\tdefault: cycle_count <= cycle_count + 1;\n\t\t\tendcase\n\t\t\tcase ({rd_wen, rd_waddr})\n\t\t\t\t{1'b1, CSR_MINSTRET}: instr_count <= {instr_count[63:32], rd_wdata};\n\t\t\t\t{1'b1, CSR_MINSTRETH}: instr_count <= {rd_wdata, instr_count[31:0]};\n\t\t\t\tdefault: instr_count <= (instr_complete)?(instr_count + 1):instr_count;\n\t\t\tendcase\n\t\t\tif (trap) begin\n\t\t\t\tmpie <= mie;\n\t\t\t\tmie <= 1'b0;\n\t\t\tend\n\t\t\tif (tret) begin\n\t\t\t\tmie <= mpie;\n\t\t\t\tmpie <= 1'b0;\n\t\t\tend\n\t\t\tif (rd_wen && rd_waddr == CSR_DEP_LO && !dep_lo_r[1]) begin\n\t\t\t\tdep_lo_r <= rd_wdata;\n\t\t\tend\n\t\t\tif (rd_wen && rd_waddr == CSR_DEP_HI && !dep_hi_r[1]) begin\n\t\t\t\tdep_hi_r <= rd_wdata;\n\t\t\tend\n\t\t\tif (rd_wen && rd_waddr == CSR_MTVEC) begin\n\t\t\t\tmtvec_r <= rd_wdata;\n\t\t\tend\n\t\t\tif (rd_wen && rd_waddr == CSR_MIE) begin\n\t\t\t\tmeie <= rd_wdata[11];\n\t\t\tend\n\t\t\tif (rd_wen && rd_waddr == CSR_MSTATUS) begin\n\t\t\t\tmie <= rd_wdata[3];\n\t\t\t\tmpie <= rd_wdata[7];\n\t\t\tend\n\t\tend\n\tend\n\talways @(posedge clock) begin\n\t\tif (rd_wen) begin\n\t\t\tif (|rd_waddr) begin\n\t\t\t\tregs[rd_waddr] <= rd_wdata;\n\t\t\tend else begin\n\t\t\t\tif (rd_waddr != 0) begin\n\t\t\t\t\t$display(\"Warning: skipping write to %0d\", rd_waddr);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\t\tcase (ra_raddr)\n\t\t\t6'b0: ra_rdata <= {32{1'b0}};\n\t\t\tCSR_MVENDORID: ra_rdata <= VENDORID;\n\t\t\tCSR_MARCHID: ra_rdata <= ARCHID;\n\t\t\tCSR_MIMPID: ra_rdata <= IMPID;\n\t\t\tCSR_MHARTID: ra_rdata <= HARTID;\n\t\t\tCSR_MISA: ra_rdata <= {2'b01, ISA[29:0]};\n\t\t\tCSR_MIE: ra_rdata <= {20'b0, meie, 11'b0};\n\t\t\tCSR_MCYCLE: ra_rdata <= cycle_count[31:0];\n\t\t\tCSR_MCYCLEH: ra_rdata <= cycle_count[63:32];\n\t\t\tCSR_MINSTRET: ra_rdata <= instr_count[31:0];\n\t\t\tCSR_MINSTRETH: ra_rdata <= instr_count[63:32];\n\t\t\tCSR_MTVEC: ra_rdata <= mtvec_r;\n\t\t\tCSR_MSCRATCH: ra_rdata <= mscratch;\n\t\t\tCSR_MIP: ra_rdata <= {20'b0, irq, 11'b0};\n\t\t\tdefault: ra_rdata <= regs[ra_raddr[5:0]];\n\t\tendcase\n\t\tcase (rb_raddr)\n\t\t\t0: rb_rdata <= {32{1'b0}};\n\t\t\tCSR_MVENDORID: rb_rdata <= VENDORID;\n\t\t\tCSR_MARCHID: rb_rdata <= ARCHID;\n\t\t\tCSR_MIMPID: rb_rdata <= IMPID;\n\t\t\tCSR_MHARTID: rb_rdata <= HARTID;\n\t\t\tCSR_MISA: rb_rdata <= {2'b01, ISA[29:0]};\n\t\t\tCSR_MIE: rb_rdata <= {20'b0, meie, 11'b0};\n\t\t\tCSR_MSTATUS: rb_rdata <= {{24{1'b0}}, mpie, {3{1'b0}}, mie, {3{1'b0}}};\n\t\t\tCSR_MCYCLE: rb_rdata <= cycle_count[31:0];\n\t\t\tCSR_MCYCLEH: rb_rdata <= cycle_count[63:32];\n\t\t\tCSR_MINSTRET: rb_rdata <= instr_count[31:0];\n\t\t\tCSR_MINSTRETH: rb_rdata <= instr_count[63:32];\n\t\t\tCSR_MTVEC: rb_rdata <= mtvec_r;\n\t\t\tCSR_MSCRATCH: rb_rdata <= mscratch;\n\t\t\tCSR_MIP: rb_rdata <= {20'b0, irq, 11'b0};\n\t\t\tdefault: rb_rdata <= regs[rb_raddr[5:0]];\n\t\tendcase\n\tend\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_regfile",
      "length": 5211,
      "id": 8
    },
    {
      "text": "module fwrisc_rv32i #(\n\tparameter[31:0] VENDORID = 0,\n\tparameter[31:0] ARCHID = 0,\n\tparameter[31:0] IMPID = 0,\n\tparameter[31:0] HARTID = 0\n\t)(\n\tinput clock,\n\tinput reset,\n\toutput[31:0] iaddr,\n\tinput[31:0] idata,\n\toutput ivalid,\n\tinput iready,\n\toutput dvalid,\n\toutput[31:0] daddr,\n\toutput[31:0] dwdata,\n\toutput[3:0] dwstb,\n\toutput dwrite,\n\tinput[31:0] drdata,\n\tinput dready,\n\tinput irq);\n\tfwrisc #(\n\t\t.ENABLE_COMPRESSED(0),\n\t\t.ENABLE_MUL_DIV(0),\n\t\t.ENABLE_DEP(0),\n\t\t.ENABLE_COUNTERS(1),\n\t\t.VENDORID(VENDORID),\n\t\t.ARCHID(ARCHID),\n\t\t.IMPID(IMPID),\n\t\t.HARTID(HARTID)\n\t) u_core (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t.iaddr(iaddr),\n\t\t.idata(idata),\n\t\t.ivalid(ivalid),\n\t\t.iready(iready),\n\t\t.dvalid(dvalid),\n\t\t.daddr(daddr),\n\t\t.dwdata(dwdata),\n\t\t.dwstb(dwstb),\n\t\t.dwrite(dwrite),\n\t\t.drdata(drdata),\n\t\t.dready(dready),\n\t\t.irq (irq));\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_rv32i",
      "length": 834,
      "id": 9
    },
    {
      "text": "module fwrisc_tracer (\n\tinput clock,\n\tinput reset,\n\tinput [31:0] pc,\n\tinput [31:0] instr,\n\tinput ivalid,\n\tinput [5:0] ra_raddr,\n\tinput [31:0] ra_rdata,\n\tinput [5:0] rb_raddr,\n\tinput [31:0] rb_rdata,\n\tinput [5:0] rd_waddr,\n\tinput [31:0] rd_wdata,\n\tinput rd_write,\n\tinput [31:0] maddr,\n\tinput [31:0] mdata,\n\tinput [3:0] mstrb,\n\tinput mwrite,\n\tinput mvalid);\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc_tracer",
      "length": 365,
      "id": 10
    },
    {
      "text": "module fwrisc #(\n\tparameter ENABLE_COMPRESSED=1,\n\tparameter ENABLE_MUL_DIV=1,\n\tparameter ENABLE_DEP=1,\n\tparameter ENABLE_COUNTERS=1,\n\tparameter[31:0] VENDORID = 0,\n\tparameter[31:0] ARCHID = 0,\n\tparameter[31:0] IMPID = 0,\n\tparameter[31:0] HARTID = 0\n\t)(\n\tinput clock,\n\tinput reset,\n\toutput[31:0] iaddr,\n\tinput[31:0] idata,\n\toutput ivalid,\n\tinput iready,\n\toutput dvalid,\n\toutput[31:0] daddr,\n\toutput[31:0] dwdata,\n\toutput[3:0] dwstb,\n\toutput dwrite,\n\tinput[31:0] drdata,\n\tinput dready,\n\tinput irq);\n\twire[31:0] pc;\n\twire[31:0] pc_seq;\n\twire fetch_valid;\n\twire instr_complete;\n\twire trap;\n\twire tret;\n\twire[31:0] instr;\n\twire instr_c;\n\twire int_reset;\n\twire soft_reset_req;\n\treg[4:0] soft_reset_count;\n\twire[31:0] mtvec;\n\treg[31:0] tracer_pc;\n\treg[31:0] tracer_instr;\n\twire[31:0] dep_lo;\n\twire[31:0] dep_hi;\n\tassign int_reset = (reset | soft_reset_count != 0);\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tsoft_reset_count <= 0;\n\t\tend else begin\n\t\t\tif (soft_reset_req) begin\n\t\t\t\tsoft_reset_count <= 5'h1f;\n\t\t\tend else if (soft_reset_count != 0) begin\n\t\t\t\tsoft_reset_count <= soft_reset_count - 1;\n\t\t\tend\n\t\tend\n\tend\n\twire decode_complete;\n\tfwrisc_fetch #(\n\t\t.ENABLE_COMPRESSED (ENABLE_COMPRESSED)\n\t) u_fetch (\n\t\t.clock (clock),\n\t\t.reset (int_reset),\n\t\t.next_pc (pc),\n\t\t.next_pc_seq (pc_seq),\n\t\t.iaddr (iaddr),\n\t\t.idata (idata),\n\t\t.ivalid (ivalid),\n\t\t.iready (iready),\n\t\t.fetch_valid (fetch_valid),\n\t\t.decode_complete (decode_complete),\n\t\t.instr (instr),\n\t\t.instr_c (instr_c));\n\twire[31:0] ra_raddr;\n\twire[31:0] ra_rdata;\n\twire[31:0] rb_raddr;\n\twire[31:0] rb_rdata;\n\twire decode_valid;\n\twire[31:0] op_a;\n\twire[31:0] op_b;\n\twire[31:0] op_c;\n\twire[3:0] op;\n\twire[5:0] rd_raddr;\n\twire[4:0] op_type;\n\tfwrisc_decode #(\n\t\t.ENABLE_COMPRESSED (ENABLE_COMPRESSED)\n\t) u_decode (\n\t\t.clock (clock),\n\t\t.reset (int_reset),\n\t\t.fetch_valid (fetch_valid),\n\t\t.decode_complete (decode_complete),\n\t\t.instr_i (instr),\n\t\t.instr_c (instr_c),\n\t\t.pc (pc),\n\t\t.ra_raddr (ra_raddr),\n\t\t.ra_rdata (ra_rdata),\n\t\t.rb_raddr (rb_raddr),\n\t\t.rb_rdata (rb_rdata),\n\t\t.decode_valid (decode_valid),\n\t\t.exec_complete (instr_complete),\n\t\t.op_a (op_a),\n\t\t.op_b (op_b),\n\t\t.op_c (op_c),\n\t\t.op (op),\n\t\t.rd_raddr (rd_raddr),\n\t\t.op_type (op_type));\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\ttracer_pc <= 0;\n\t\t\ttracer_instr <= 0;\n\t\tend else begin\n\t\t\tif (decode_valid) begin\n\t\t\t\ttracer_pc <= pc;\n\t\t\t\ttracer_instr <= instr;\n\t\t\tend\n\t\tend\n\tend\n\twire[5:0] rd_waddr;\n\twire[31:0] rd_wdata;\n\twire rd_wen;\n\twire meie;\n\twire mie;\n\tfwrisc_exec #(\n\t\t.ENABLE_COMPRESSED (ENABLE_COMPRESSED),\n\t\t.ENABLE_MUL_DIV (ENABLE_MUL_DIV)\n\t) u_exec (\n\t\t.clock (clock),\n\t\t.reset (int_reset),\n\t\t.decode_valid (decode_valid),\n\t\t.instr_complete (instr_complete),\n\t\t.trap (trap),\n\t\t.tret (tret),\n\t\t.instr_c (instr_c),\n\t\t.op_type (op_type),\n\t\t.op_a (op_a),\n\t\t.op_b (op_b),\n\t\t.op (op),\n\t\t.op_c (op_c),\n\t\t.rd (rd_raddr),\n\t\t.rd_waddr (rd_waddr),\n\t\t.rd_wdata (rd_wdata),\n\t\t.rd_wen (rd_wen),\n\t\t.pc (pc),\n\t\t.pc_seq (pc_seq),\n\t\t.mtvec (mtvec),\n\t\t.dep_lo (dep_lo),\n\t\t.dep_hi (dep_hi),\n\t\t.dvalid (dvalid),\n\t\t.daddr (daddr),\n\t\t.dwrite (dwrite),\n\t\t.dwdata (dwdata),\n\t\t.dwstb (dwstb),\n\t\t.drdata (drdata),\n\t\t.dready (dready),\n\t\t.irq (irq),\n\t\t.meie (meie),\n\t\t.mie (mie));\n\tfwrisc_regfile #(\n\t\t.ENABLE_COUNTERS (ENABLE_COUNTERS),\n\t\t.ENABLE_DEP (ENABLE_DEP),\n\t\t.VENDORID (VENDORID),\n\t\t.ARCHID (ARCHID),\n\t\t.IMPID (IMPID),\n\t\t.HARTID (HARTID),\n\t\t.ISA ({\n\t\t\t2'b01,\n\t\t\t4'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b1,\n\t\t\t(ENABLE_MUL_DIV)?1'b1:1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b1,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0,\n\t\t\t(ENABLE_COMPRESSED)?1'b1:1'b0,\n\t\t\t1'b0,\n\t\t\t1'b0})\n\t) u_regfile (\n\t\t.clock (clock),\n\t\t.reset (int_reset),\n\t\t.soft_reset_req (soft_reset_req),\n\t\t.instr_complete (instr_complete),\n\t\t.trap (trap),\n\t\t.tret (tret),\n\t\t.irq (irq),\n\t\t.ra_raddr (ra_raddr),\n\t\t.ra_rdata (ra_rdata),\n\t\t.rb_raddr (rb_raddr),\n\t\t.rb_rdata (rb_rdata),\n\t\t.rd_waddr (rd_waddr),\n\t\t.rd_wdata (rd_wdata),\n\t\t.rd_wen (rd_wen),\n\t\t.dep_lo (dep_lo),\n\t\t.dep_hi (dep_hi),\n\t\t.mtvec (mtvec),\n\t\t.meie (meie),\n\t\t.mie (mie));\n\tfwrisc_tracer u_tracer (\n\t\t.clock (clock),\n\t\t.reset (reset),\n\t\t.pc (tracer_pc),\n\t\t.instr (tracer_instr),\n\t\t.ivalid (instr_complete),\n\t\t.ra_raddr (ra_raddr),\n\t\t.ra_rdata (ra_rdata),\n\t\t.rb_raddr (rb_raddr),\n\t\t.rb_rdata (rb_rdata),\n\t\t.rd_waddr (rd_waddr),\n\t\t.rd_wdata (rd_wdata),\n\t\t.rd_write (rd_wen),\n\t\t.maddr (daddr),\n\t\t.mdata ((dwrite)?dwdata:drdata),\n\t\t.mstrb (dwstb),\n\t\t.mwrite (dwrite),\n\t\t.mvalid ((dready && dvalid)));\nendmodule",
      "source": "Github - Featherweight-IP/fwrisc - fwrisc",
      "length": 4528,
      "id": 11
    },
    {
      "text": "`include \"flops.svh\"\n`include \"aes.svh\"\nmodule aes_cipher\n#(\n\tparameter Nk=4,\n\tparameter Nr=Nk+6\n) (\n\tinput logic clk,\n\tinput logic rst_n,\n\tinput logic [127:0] k_sch [0:Nr],\n\tinput logic load,\n\tinput logic [127:0] pt,\n\toutput logic [127:0] ct,\n\toutput logic valid\n);\nlogic [127:0] state [0:Nr];\nlogic [127:0] s_box [1:Nr];\nlogic [127:0] s_row [1:Nr];\nlogic [127:0] m_col [1:Nr-1];\nlogic valids [0:Nr];\nalways_comb ct = state[Nr];\nalways_comb valid = valids[Nr];\n`DFFEN(state[0], AddRoundKey(pt, k_sch[0]), load, clk)\n`DFF_ARN(valids[0], load, clk, rst_n, 1'b0)\ngenerate\n\tfor (genvar i = 1; i < Nr; ++i) begin: round\n\t\talways_comb s_box[i] = SubBytes(state[i-1]);\n\t\talways_comb s_row[i] = ShiftRows(s_box[i]);\n\t\talways_comb m_col[i] = MixColumns(s_row[i]);\n\t\t`DFFEN(state[i], AddRoundKey(m_col[i], k_sch[i]), valids[i-1], clk)\n\t\t`DFF_ARN(valids[i], valids[i-1], clk, rst_n, 1'b0)\n\tend: round\nendgenerate\nalways_comb s_box[Nr] = SubBytes(state[Nr-1]);\nalways_comb s_row[Nr] = ShiftRows(s_box[Nr]);\n`DFFEN(state[Nr], AddRoundKey(s_row[Nr], k_sch[Nr]), valids[Nr-1], clk)\n`DFF_ARN(valids[Nr], valids[Nr-1], clk, rst_n, 1'b0)\nendmodule: aes_cipher",
      "source": "Github - cjdrake/AES - aes_cipher",
      "length": 1142,
      "id": 12
    },
    {
      "text": "`include \"flops.svh\"\nmodule aes_decrypt\n#(\n\tparameter Nk=4,\n\tparameter Nr=Nk+6\n) (\n\tinput logic clk,\n\tinput logic rst_n,\n\tinput logic [32*Nk-1:0] key,\n\tinput logic load,\n\tinput logic [127:0] ct,\n\toutput logic [127:0] pt,\n\toutput logic valid\n);\nlogic [127:0] k_sch [0:Nr];\naes_key_expand #(Nk) key_expand(.*);\naes_inv_cipher #(Nk) inv_cipher(.*);\nendmodule: aes_decrypt",
      "source": "Github - cjdrake/AES - aes_decrypt",
      "length": 368,
      "id": 13
    },
    {
      "text": "`include \"flops.svh\"\nmodule aes_encrypt\n#(\n\tparameter Nk=4,\n\tparameter Nr=Nk+6\n) (\n\tinput logic clk,\n\tinput logic rst_n,\n\tinput logic [32*Nk-1:0] key,\n\tinput logic load,\n\tinput logic [127:0] pt,\n\toutput logic [127:0] ct,\n\toutput logic valid\n);\nlogic [127:0] k_sch [0:Nr];\naes_key_expand #(Nk) key_expand(.*);\naes_cipher #(Nk) cipher(.*);\nendmodule: aes_encrypt",
      "source": "Github - cjdrake/AES - aes_encrypt",
      "length": 360,
      "id": 14
    },
    {
      "text": "`include \"flops.svh\"\n`include \"aes.svh\"\nmodule aes_inv_cipher\n#(\n\tparameter Nk=4,\n\tparameter Nr=Nk+6\n) (\n\tinput logic clk,\n\tinput logic rst_n,\n\tinput logic [127:0] k_sch [0:Nr],\n\tinput logic load,\n\tinput logic [127:0] ct,\n\toutput logic [127:0] pt,\n\toutput logic valid\n);\nlogic [127:0] istate [0:Nr];\nlogic [127:0] is_row [0:Nr-1];\nlogic [127:0] is_box [0:Nr-1];\nlogic [127:0] ik_add [1:Nr-1];\nlogic valids [0:Nr];\nalways_comb pt = istate[0];\nalways_comb valid = valids[0];\n`DFFEN(istate[Nr], AddRoundKey(ct, k_sch[Nr]), load, clk)\n`DFF_ARN(valids[Nr], load, clk, rst_n, 1'b0)\ngenerate\n\tfor (genvar i = (Nr-1); i > 0; --i) begin: round\n\t\talways_comb is_row[i] = InvShiftRows(istate[i+1]);\n\t\talways_comb is_box[i] = InvSubBytes(is_row[i]);\n\t\talways_comb ik_add[i] = AddRoundKey(is_box[i], k_sch[i]);\n\t\t`DFFEN(istate[i], InvMixColumns(ik_add[i]), valids[i+1], clk)\n\t\t`DFF_ARN(valids[i], valids[i+1], clk, rst_n, 1'b0)\n\tend: round\nendgenerate\nalways_comb is_row[0] = InvShiftRows(istate[1]);\nalways_comb is_box[0] = InvSubBytes(is_row[0]);\n`DFFEN(istate[0], AddRoundKey(is_box[0], k_sch[0]), valids[1], clk)\n`DFF_ARN(valids[0], valids[1], clk, rst_n, 1'b0)\nendmodule: aes_inv_cipher",
      "source": "Github - cjdrake/AES - aes_inv_cipher",
      "length": 1178,
      "id": 15
    },
    {
      "text": "`include \"aes.svh\"\nmodule aes_key_expand\n#(\n\tparameter Nk=4,\n\tparameter Nr=Nk+6\n) (\n\tinput logic [32*Nk-1:0] key,\n\toutput logic [127:0] k_sch [0:Nr]\n);\nlogic [31:0] temp [4*(Nr+1)];\ngenerate\n\tfor (genvar i = 0; i < Nk; ++i) begin\n\t\talways_comb\n\t\t\ttemp[i] = key[32*i+:32];\n\tend\n\tfor (genvar i = Nk; i < 4*(Nr+1); ++i) begin\n\t\tif (i % Nk == 0)\n\t\t\talways_comb\n\t\t\t\ttemp[i] = temp[i-Nk]\n\t\t\t\t\t\t^ SubWord(RotWord(temp[i-1]))\n\t\t\t\t\t\t^ {24'h0, RCON[i/Nk]};\n\t\telse if (Nk > 6 && (i % Nk == 4))\n\t\t\talways_comb\n\t\t\t\ttemp[i] = temp[i-Nk] ^ SubWord(temp[i-1]);\n\t\telse\n\t\t\talways_comb\n\t\t\t\ttemp[i] = temp[i-Nk] ^ temp[i-1];\n\tend\nendgenerate\ngenerate\n\tfor (genvar i = 0; i <= Nr; ++i) begin\n\t\talways_comb\n\t\t\tk_sch[i] = {temp[4*i+3], temp[4*i+2], temp[4*i+1], temp[4*i+0]};\n\tend\nendgenerate\nendmodule: aes_key_expand",
      "source": "Github - cjdrake/AES - aes_key_expand",
      "length": 795,
      "id": 16
    },
    {
      "text": "module ACC_CLK_GEN\n#(parameter int ACC_SIZE = 12,\n\tint FCW = 59\n)\n(\n\toutput logic clk_o,\n\tinput wire logic clk_i, rst_i\n);\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\tlogic [ACC_SIZE : 0] acc_reg;\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\t acc_reg <= '0;\n\t\tend\n\t\telse begin\n\t\t\tacc_reg <= acc_reg [ACC_SIZE-1:0] + FCW;\n\t\tend\n\tend\n\talways_ff @(posedge clk_i) begin\n\t\t\tif (rst_i) begin\n\t\t\t\t clk_o <= '0;\n\t\t\tend\n\t\t\telse if (acc_reg[ACC_SIZE]) begin\n\t\t\t\tclk_o <= ~clk_o;\n\t\t\tend\n\tend\nendmodule\n\n",
      "source": "Github - degas91/UART_Controller - ACC_CLK_GEN",
      "length": 495,
      "id": 17
    },
    {
      "text": "module EDGE_TO_PULSE\n#(parameter string PULSE_TYPE = \"redge\"\n)\n(\n\toutput logic pulse_o,\n\tinput wire logic edge_i, clk_i, rst_i\n);\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\tlogic ff_out;\n\tgenerate if (PULSE_TYPE == \"redge\") begin\n\t\t\t\talways_ff @(posedge clk_i) begin\n\t\t\t\t\tif (rst_i == 1) begin\n\t\t\t\t\t\tff_out <= '0;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tff_out <= edge_i;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tassign pulse_o = edge_i && (~ff_out);\n\t\t\tend\n\t\t\telse if (PULSE_TYPE == \"fedge\") begin\n\t\t\t\talways_ff @(posedge clk_i) begin\n\t\t\t\t\tif (rst_i == 1) begin\n\t\t\t\t\t\tff_out <= '0;\n\t\t\t\t\tend\n\t\t\t\t\telse begin\n\t\t\t\t\t\tff_out <= edge_i;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tassign pulse_o = (~edge_i) && (ff_out);\n\t\t\tend\n\tendgenerate\nendmodule\n",
      "source": "Github - degas91/UART_Controller - EDGE_TO_PULSE",
      "length": 685,
      "id": 18
    },
    {
      "text": "module SYNC\n#(parameter int WIDTH = 1,\n\tint PIPE_LENGTH = 2\n)\n(\n\toutput logic [WIDTH-1:0] sync_sig_o,\n\tinput wire logic [WIDTH-1:0] sig_i,\n\tinput wire logic dest_clk_i\n);\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\tlogic [PIPE_LENGTH-1:0] sync_sig;\n\tgenerate\n\t\tfor ( genvar i = 0 ; i<WIDTH ; i++ ) begin\n\t\t\talways_ff @(posedge dest_clk_i) begin\n\t\t\t\tsync_sig <= {sync_sig,sig_i[i]};\n\t\t\tend\n\t\t\tassign sync_sig_o[i] = sync_sig[PIPE_LENGTH-1];\n\t\tend\n\tendgenerate\nendmodule\n\n",
      "source": "Github - degas91/UART_Controller - SYNC",
      "length": 462,
      "id": 19
    },
    {
      "text": "module SYNC_DEBOUNCE\n#(parameter int debounce_prd = 50\n)\n(\n\toutput logic sync_sig_o,\n\tinput wire logic raw_sig_i, dest_clk_i, dest_rst_i\n);\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\tlogic temp_sig, sync_sig, count_en;\n\tint count;\n\talways_ff@ (posedge dest_clk_i) begin\n\t\tif (dest_rst_i) begin\n\t\t\ttemp_sig <= '0;\n\t\tend\n\t\telse begin\n\t\t\ttemp_sig <= sync_sig;\n\t\tend\n\tend\n\tassign count_en = sync_sig ^ temp_sig;\n\talways_ff@ (posedge dest_clk_i) begin\n\t\tif (dest_rst_i) begin\n\t\t\tcount <= 0;\n\t\tend else begin\n\t\t\tif (count_en) begin\n\t\t\t\tcount <= 0;\n\t\t\tend\n\t\t\telse if (count == debounce_prd-4) begin\n\t\t\t\tsync_sig_o <= temp_sig;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tcount <= count + 1;\n\t\t\tend\n\t\tend\n\tend\n\tSYNC #(\n\t\t.WIDTH(1),\n\t\t.PIPE_LENGTH(2)\n\t\t)\n\tCDC_SYNC (\n\t\t.dest_clk_i(dest_clk_i),\n\t\t.sig_i(raw_sig_i),\n\t\t.sync_sig_o(sync_sig)\n\t\t);\nendmodule\n",
      "source": "Github - degas91/UART_Controller - SYNC_DEBOUNCE",
      "length": 819,
      "id": 20
    },
    {
      "text": "package UART_pkg;\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\ttypedef enum logic [2:0]\n\t{RX_IDLE    = 3'b000,\n\tRX_START    = 3'b001,\n\tRX_READ     = 3'b011,\n\tRX_STOP     = 3'b010,\n\tRX_STOP2    = 3'b110,\n\tRX_ERROR    = 3'b111,\n\tRX_EOM      = 3'b101,\n\tRX_XXX      = 3'bXXX } uart_rx_e;\n\ttypedef enum logic [1:0]\n\t{TX_IDLE    = 2'b00,\n\tTX_START    = 2'b01,\n\tTX_XMIT     = 2'b11,\n\tTX_XXX      = 2'bXX } uart_tx_e;\nendpackage\n",
      "source": "Github - degas91/UART_Controller - UART_pkg",
      "length": 412,
      "id": 21
    },
    {
      "text": "module UART_RCVR \n#(parameter DATA_WIDTH = 8\n) \n(\n\toutput logic data_rdy_o, data_err_o,\n\toutput logic [DATA_WIDTH-1 : 0] rcvr_data_o,\n\tinput wire logic baud_i, serial_i, data_err_clr_i, data_rdy_clr_i, clk_i, rst_i\n);\n\ttimeunit 1ns;\n\ttimeprecision 1ps;\n\timport UART_pkg::*;\n\tuart_rx_e state, next;\n\tlogic [DATA_WIDTH-1 : 0] shift_reg;\n\tlogic m_data_rdy,m_data_err;\n\tlogic baud_fedg,data_rdy,data_err;\n\tint bit_count;\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\tstate <= RX_IDLE;\n\t\tend\n\t\telse begin\n\t\t\tstate <= next;\n\t\tend\n\tend\n\talways_comb begin\n\t\tcase (state)\n\t\t\tRX_IDLE:\n\t\t\t\tif (!baud_i && !serial_i) begin\n\t\t\t\t\tnext = RX_START;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tnext = RX_IDLE;\n\t\t\t\tend\n\t\t\tRX_START: if (baud_i) next = RX_READ;\n\t\t\t\t\telse next = RX_START;\n\t\t\tRX_READ: if (bit_count  == DATA_WIDTH && baud_i) next = RX_STOP;\n\t\t\t\t\telse next = RX_READ;\n\t\t\tRX_STOP: if (!serial_i && !baud_i) next = RX_ERROR;\n\t\t\t\t\telse if (serial_i && !baud_i) next = RX_STOP2;\n\t\t\t\t\telse next = RX_STOP;\n\t\t\tRX_STOP2: if (!serial_i && baud_i) next = RX_ERROR;\n\t\t\t\t\telse if (serial_i && baud_i) next = RX_EOM;\n\t\t\t\t\telse next = RX_STOP2;\n\t\t\tRX_ERROR: next = RX_EOM;\n\t\t\tRX_EOM: next = RX_IDLE;\n\t\t\tdefault: next = RX_XXX;\n\t\tendcase\n\tend\n\talways_comb begin\n\t\t{m_data_err,m_data_rdy} = '0;\n\t\tcase (state)\n\t\t\tRX_IDLE: ;\n\t\t\tRX_START: ;\n\t\t\tRX_READ: ;\n\t\t\tRX_STOP: ;\n\t\t\tRX_STOP2: ;\n\t\t\tRX_ERROR: m_data_err  = '1;\n\t\t\tRX_EOM: m_data_rdy  = '1;\n\t\t\tdefault: {m_data_err,m_data_rdy} = 'x;\n\t\tendcase\n\tend\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\tdata_rdy <= '0;\n\t\t\tdata_err <= '0;\n\t\tend\n\t\telse begin\n\t\t\tdata_rdy <= m_data_rdy;\n\t\t\tdata_err <= m_data_err;\n\t\tend\n\tend\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\tshift_reg <= '0;\n\t\t\tbit_count <= '0;\n\t\tend\n\t\telse begin\n\t\t\tif (baud_fedg && (state == RX_READ)) begin\n\t\t\t\tshift_reg <= {serial_i, shift_reg[DATA_WIDTH-1:1]};\n\t\t\t\tbit_count <= bit_count+1;\n\t\t\tend\n\t\t\telse if (state == RX_IDLE) begin\n\t\t\t\tbit_count <= '0;\n\t\t\tend\n\t\tend\n\tend\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\tdata_rdy_o <= '0;\n\t\t\trcvr_data_o <= '0;\n\t\tend\n\t\telse begin\n\t\t\tif (data_rdy == 1) begin\n\t\t\t\tdata_rdy_o <= '1;\n\t\t\t\trcvr_data_o <= shift_reg;\n\t\t\tend\n\t\t\telse if (data_rdy_clr_i == 1) begin\n\t\t\t\tdata_rdy_o <= '0;\n\t\t\tend\n\t\tend\n\tend\n\talways_ff @(posedge clk_i) begin\n\t\tif (rst_i) begin\n\t\t\tdata_err_o <= '0;\n\t\tend\n\t\telse begin\n\t\t\tif (data_err == 1) begin\n\t\t\t\tdata_err_o <= '1;\n\t\t\tend\n\t\t\telse if (data_err_clr_i == 1) begin\n\t\t\t\tdata_err_o <= '0;\n\t\t\tend\n\t\tend\n\tend\n\tEDGE_TO_PULSE #(\n\t.PULSE_TYPE(\"fedge\")\n\t)\n\tNEGEDGE_DTCT (\n\t.pulse_o(baud_fedg),\n\t.edge_i(baud_i),\n\t.clk_i(clk_i),\n\t.rst_i(rst_i)\n\t);\nendmodule\n",
      "source": "Github - degas91/UART_Controller - UART_RCVR",
      "length": 2628,
      "id": 22
    },
    {
      "text": "module UART_TOP\n#(parameter DATA_WIDTH = 8, ACC_SIZE = 32, FCW = 9895605\n)\n(\n\toutput logic data_rdy_o, data_err_o, serial_o, busy_o,\n\toutput logic [DATA_WIDTH-1:0] rcvr_data_o,\n\tinput wire logic serial_i, start_tx_i, clk_i, rst_i, data_rdy_clr_i, data_err_clr_i,\n\tinput wire logic [DATA_WIDTH-1:0] xmit_data_i\n);\n\ttimeunit 1nss;\n\ttimeprecision 1ps;\n\tlogic baud_clk, serial_sync;\n\tUART_RCVR #(\n\t\t.DATA_WIDTH(DATA_WIDTH)\n\t\t)\n\tRCVR (\n\t\t.data_rdy_o(data_rdy_o),\n\t\t.data_err_o(data_err_o),\n\t\t.rcvr_data_o(rcvr_data_o),\n\t\t.baud_i(baud_clk),\n\t\t.serial_i(serial_sync),\n\t\t.data_err_clr_i(data_err_clr_i),\n\t\t.data_rdy_clr_i(data_rdy_clr_i),\n\t\t.clk_i(clk_i),\n\t\t.rst_i(rst_i)\n\t\t);\n\tUART_XMTR #(\n\t\t.DATA_WIDTH(DATA_WIDTH)\n\t\t)\n\tXMTR (\n\t\t.xmit_data_i(xmit_data_i),\n\t\t.start_tx_i(start_tx_i),\n\t\t.baud_i(baud_clk),\n\t\t.clk_i(clk_i),\n\t\t.rst_i(rst_i),\n\t\t.busy_o(busy_o),\n\t\t.serial_o(serial_o)\n\t\t);\n\tSYNC_DEBOUNCE #(\n\t\t.debounce_prd(50)\n\t\t)\n\tSERIAL_I_DEBOUNCE (\n\t\t.sync_sig_o(serial_sync),\n\t\t.raw_sig_i(serial_i),\n\t\t.dest_clk_i(clk_i),\n\t\t.dest_rst_i(rst_i)\n\t\t);\n\t(* use_dsp =\"yes\" *) ACC_CLK_GEN #(\n\t\t.ACC_SIZE(ACC_SIZE),\n\t\t.FCW (FCW)\n\t\t)\n\tBAUD_GEN (\n\t\t.clk_o(baud_clk),\n\t\t.clk_i(clk_i),\n\t\t.rst_i(rst_i)\n\t\t);\nendmodule\n",
      "source": "Github - degas91/UART_Controller - UART_TOP",
      "length": 1198,
      "id": 23
    }
  ]
}